Use raw strings in lint.py to fix a Python error.

The DC ZVA instruction allows zeroing areas of memory, typically at block sizes
of 64 bytes per instance. Add support for this in all components, with tests.

Positional arguments to printf (eg. %1$s) are not allowed on Windows, so remove
uses of this in the disassembler, replacing them with an extension to the
existing NEONFormatDecoder class.

Patch prompted by https://github.com/Linaro/vixl/pull/122

Extend the SVE PMULL instructions to support Q destination elements when the
CPU feature is supported.

Most MOPS sequences implement one of options "A" or "B", with slightly
different flags in each case. Some `cpy` sequences also permit either
forward or backward iteration, with different register results.

This relies on a new overloaded form of `Equal64` that checks that a
register matches any one of the listed reference values.

In addition, renumber registers to avoid the use of `x16` in a couple of
tests, because this is a MacroAssembler scratch register and could cause
issues in the future.

Add support for two Neon SM4 accelerating instructions.

Some Neon instructions such as sqrdmulh only operate on H and S-sized elements.
The disassembler already restricts this, so extend checks to the simulator.
Additionally, reuse the new register/index extraction function in other parts of
the simulator.

Veneers were applied to backward branches too early, using only a quarter of the
range available for the branch. This was caused by confusion over the units the
range function expects; it accepts an offset in instructions.

Correct this and test veneers are applied only beyond the limit of the branch
range.

Previously, we would hit a VIXL_UNIMPLEMENTED, but this appears as a
test failure. Instead, use the "SKIPPED" marker, which is detected and
presented by `test.py`.

These encodings are "RESERVED".

The simulator will be updated in a subsequent commit, as part of a
refactoring of `VisitNEONScalar3Same` (to match the disassembler).

These instructions leave some bits of NZCV unmodified, so we need to
initialise them to make the behaviour consistent.

Collisions are unlikely, but there are enough PAuth tests that we
commonly see failures on hardware.

https://github.com/llvm/llvm-project/issues/108722

This is in order to prevent one instruction from appearing to refer to
two litersls.

Moving is permitted as it does not cause the same problem, and can be
useful to allow containers of Literal

Add a new document explaining the range limits of branches and literal-handling
instructions for AArch32 and AArch64, and the veneering capabilities of the
macro assembler.

Backwards (ie. bound) conditional branches that were out of range of the
immediate encoded in the instruction would fail, so apply a veneer to
these instruction by inverting the condition and using an unconditional branch.

Extend MTE irg test to check that all tags expected have been allocated.
Previously, the test wasn't detecting a case where the upper half of the range
was still unallocated.

Refactor assembler tests for fcvt by providing a helper function, extracting the
common cases, and moving the remainder to clearer input versus expected result
comparisons.

C++20's DR 2237 forbids using template-ids in constructors and
destructors, and GCC 14 started warning about this.

Add support for seven Neon SM3 accelerating instructions.

Add support for four Neon AES accelerating instructions.

This silences (for example) Python 3.12.3 warnings about invalid escape
sequences in some of our regular expressions.

Add support for four Neon SHA-512 accelerating instructions.

Add support for four Neon SHA-2 accelerating instructions.

Add support for six Neon SHA-1 accelerating instructions.

Add support for Neon BCAX, EOR3, RAX1 and XAR instructions, used to accelerate
SHA-3.

Add support for Guarded Control Stacks in all components, and allow allocating
new stacks in the simulator.

In two's-complement representation, the negation of the minimum value of a
signed type can't be represented. Detect and elide inversion for these cases
in ccmp, ccmn and neg.

Disassembling some FCM, RDM and dot product instructions could report vector
types that are undefined for the associated mnemonics. Fix this and add tests.

Fix some Neon lengthening, narrowing and insertion instructions that should
zero the upper bits of SVE registers, and add regression tests.

In particular, this fixes ADDHN2, FCVTL, FCVTL2, FCVTN2, FCVTXN2,
FMOV (to d[1]), LD1 (single element), RADDHN2, RSUBHN2, SQXTN2, SQXTUN2, SUBHN2,
UQXTN2 and XTN2 for simulated systems with VL > 128 bits.

Also, enable FCMLA by-element instructions, for which code already exists but
wasn't being called in simulation.

The INS instruction inserts an element into an existing 128-bit vector, but for
systems with larger SVE registers, bits beyond the end of the vector must be
zeroed. Fix this and add a regression test.

Chris Jones authored Feb 29, 2024 and Jacob Bramley committed Apr 30, 2024

It is possible for runtimes to perform implicit checks on store
instructions as well as load instructions, therefore support
performing implicit checks on store instructions as well as loads. Do
this by returning true from memory write operations if they succeeded
and false if they failed but were handled by a signal handler.

Implicit checks on store instructions are simulated using a native
memory load because introducing an additional memory store could
change the observable behaviour of multithreaded runtimes. This means
that it is not currently possible to accurately simulate the
behaviour of implicit checks on regions with different access
permissions for reads/writes. For example: if a page has read but not
write permissions then an implicit check would not fail as the
underlying probing instruction will perform a memory read.

All memory read functions (e.g: ld1, ld2, etc...) return a value
(either std::nullopt or false) to signal that the memory read failed.
Some of these memory read functions were not being checked for
failure; fix this by checking these functions for failure.