Fix zeroing part of SVE register for Neon instructions (#97)

Fix some Neon lengthening, narrowing and insertion instructions that should
zero the upper bits of SVE registers, and add regression tests.

In particular, this fixes ADDHN2, FCVTL, FCVTL2, FCVTN2, FCVTXN2,
FMOV (to d[1]), LD1 (single element), RADDHN2, RSUBHN2, SQXTN2, SQXTUN2, SUBHN2,
UQXTN2 and XTN2 for simulated systems with VL > 128 bits.

Also, enable FCMLA by-element instructions, for which code already exists but
wasn't being called in simulation.