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  1. Feb 09, 2024
    • Martyn Capewell's avatar
      Update version to 7.0.0. · ea4fb654
      Martyn Capewell authored
      7.0.0
      ea4fb654
    • Pierre Langlois's avatar
      Ensure the `threaded_tests` module can be imported safely (#90) · accc97f1
      Pierre Langlois authored
      On MacOS, running `multiprocessing.Manager()` spawns a new process. This
      means it's not OK to run this in the global namespace, as that runs
      while modules are being resolved, before main. The multiprocessing
      guidelines [0], under "Safe importing of main module", indicate that
      multiprocessing operations may have side-effects and mustn't run at that
      point.
      
      This turns the `Test.manager` global object into a local variable. The
      manager's job is to handle shared state between processes and so its
      lifetime is tied to the shared data. That data is then tied to the
      `TestQueue` instance which runs tests in parallel and collects results.
      
      So we can wrap the parallel test queue runner with a
      `multiprocess.Manager()` context:
      
          def Run(self, ...):
            with multiprocessing.Manager() as manager:
              # Run tests in parallel with manager
      
      [0]: https://docs.python.org/3/library/multiprocessing.html#multiprocessing-programming
      accc97f1
    • mmc28a's avatar
      Fix some portability and build problems (#89) · ef2f4d15
      mmc28a authored
      Remove use of deprecated std::iterator.
      Fix colordiff use in clang_format script (from jacob.bramley@arm.com).
      Remove debugger tests from non-simulator builds.
      Update code coverage record.
      ef2f4d15
  2. Feb 01, 2024
  3. Jan 17, 2024
    • snickolls-arm's avatar
      Update tools to python3 (#85) · 2decd2cf
      snickolls-arm authored
      This updates the scripts in the tools directory to work with python3, python2
      support is now deprecated.
      
      The only significant API change is that the subprocess module works in bytes
      instead of str, the rest are mainly style changes.
      2decd2cf
  4. Dec 08, 2023
    • Chris Jones's avatar
      Update code coverage (#83) · 08574f1b
      Chris Jones authored
      Updates the code coverage log to the latest version.
      08574f1b
    • Chris Jones's avatar
      Update to C++17 (#82) · 7a2a4728
      Chris Jones authored
      Update the default build to use C++17 instead of C++14. This enables
      usage of C++17 features in VIXL.
      
      Note: this removes C++14 as a testing target as use of C++17 features
      will break building with C++14.
      7a2a4728
    • Chris Jones's avatar
      Add a debugger to VIXL simulator (#81) · a0a14395
      Chris Jones authored
      Add a basic debugger to the VIXL simulator. Once enabled (by default
      the debugger is disabled) any brk instruction encountered while
      simulating will cause the interactive debugger to be launched.
      
      The debugger supports the following features:
      - Break
      - Step
      - Continue
      - Printing registers
      - Toggling tracing
      - Switching to GDB
      a0a14395
  5. Sep 13, 2023
    • Chris Jones's avatar
      Add branch interception to VIXL simulator (#77) · 8eca2b7b
      Chris Jones authored
      * Add maybe_unused to runtime call arguments
      
      Currently runtime calls cannot be done if the function to be called
      has no parameters because the compiler will give a
      "unused-but-set-parameter" warning which is treated as an error. Fix
      this by always using the 'arguments' parameter.
      
      Change-Id: I9f4b75ea8b6ae6fe03be33cefa45fa99f5485b7a
      
      * Add branch interception to VIXL simulator
      
      Simulated AARCH64 code, that is not written in using the
      macroassembler, can branch (change the simulated PC) to arbitrary
      function addresses. This works fine if that function is AARCH64
      however if that function is a native (x86_64) C++ function then an
      error (likely SIGILL) will be thrown. To handle this case we need to
      "intercept" branches to these native (x86_64) C++ functions and
      instead either perform a runtime call to the function or provide a
      callback to manually handle the particular case.
      
      Add a mechanism to intercept functions as they are branched to
      within the VIXL simulator. This means that whenever a function X is
      branched to (e.g: bl X) instead, if provided, a callback function Y
      is called. If no callback is provided for the interception to
      function X then a runtime call will be done on function X.
      
      Branch interception objects consisting of the function to intercept:
      X, and an optional callback function Y are stored within the
      simulator and checked every unconditional branch to register.
      
      Change-Id: I874a6fa5b8f0581fe930a7a98f762031bdb2f591
      8eca2b7b
  6. Aug 15, 2023
  7. Jun 20, 2023
    • Anton Kirilov's avatar
      Improve SIMD & FP constant materialization (#74) · 279f08b5
      Anton Kirilov authored
      * Fix a code generation issue inside the MacroAssembler::Movi64bitHelper()
      method that could set the upper 64 bits of a vector register to an
      incorrect value instead of 0
      * Reduce the instructions necessary to materialize a vector constant
      by 2 when the upper 64 bits are 0, while the lower ones aren't
      * Restructure the code paths for the immediate forms of FMOV, so
      that the common case, 0, is handled first
      279f08b5
  8. Jun 14, 2023
  9. May 30, 2023
  10. May 16, 2023
  11. May 09, 2023
    • mmc28a's avatar
      Small optimisation for Assembler::Emit (#71) · 64c25fed
      mmc28a authored
      Inside Emit(), the compiler can't be sure that the pc_ field of the Assembler
      object doesn't point to itself, so it must be reloaded from the object after the
      call to memcpy, in order to advance pc_.
      
      Emit() is used by all Assembler methods, so optimise it a little by making a
      local copy of the field.
      64c25fed
  12. Mar 16, 2023
  13. Feb 24, 2023
    • Richard Neill's avatar
      Fix BIC macro assembler definition to be non-commutative (#66) · b6725cfe
      Richard Neill authored
      Without this patch, the macro assembler freely rearranges the registers
      passed for the BIC instruction to ensure the first source register is
      the same as the destination register, which it does because the
      instruction is considered to be commutative. However, the
      bit-clear instruction is non-commutative as it is the second source
      register which is negated, and so these should not be simply re-arranged
      without additional logic.
      
      Instead, define Bic to be non-commutative as part of
      VIXL_SVE_NONCOMM_ARITH_ZPZZ_LIST.
      
      Modify the tests for SVE predicated bit-clears accordingly.
      b6725cfe
    • mmc28a's avatar
      Update code coverage record (#67) · 1b2332d4
      mmc28a authored
      1b2332d4
  14. Feb 08, 2023
  15. Jan 18, 2023
  16. Jan 17, 2023
    • mmc28a's avatar
      Fix register trace involving sp and xzr (#59) · 9128d580
      mmc28a authored
      Tracing register updates for ldp instructions that use both xzr and sp would
      not print the updated stack address. This was visible when popping from the
      stack into xzr, to discard an entry. Fix this and update the trace tests.
      9128d580
  17. Jan 03, 2023
  18. Nov 18, 2022
  19. Nov 16, 2022
  20. Nov 11, 2022
  21. Nov 09, 2022
    • Mai's avatar
      instructions-aarch64: Handle destructive EXT in CanTakeSVEMovprfx (#55) · c40e2ab0
      Mai authored
      The ARM architecture manual states that a destructive SVE EXT
      instructions might be preceded by a MOVPRFX instruction, and that this
      is allowed, but that:
      
      1. The MOVPRFX instruction must be unpredicated
      2. The MOVPRFX instruction must specify the same destination as the EXT
         instruction.
      3. The destination register cannot refer to any other source operand.
      c40e2ab0
  22. Nov 02, 2022
  23. Nov 01, 2022
  24. Oct 25, 2022
  25. Oct 19, 2022
  26. Sep 27, 2022
    • Anton Kirilov's avatar
      Fix compilation with Microsoft Visual C++ (#46) · 088b01fe
      Anton Kirilov authored
      Also, fix almost all warnings with the "/W3" setting (default for
      new command-line projects), and some with "/W4" and "/Wall". The
      simulator implementation is out of scope because it uses too many
      POSIX interfaces to be usable (and in fact buildable) on Windows.
      088b01fe
  27. Sep 15, 2022
    • mmc28a's avatar
      Fix disassembly of Neon by-element instructions (#45) · 19dfd911
      mmc28a authored
      The disassembly of Neon by-element instructions, such as fmul, was not decoding
      register Vm correctly; it can be four or five bits depending on element size.
      
      Fix this and add regression tests for all affected instructions.
      19dfd911
  28. Aug 11, 2022
    • Martyn Capewell's avatar
      Merge branch 'main' into mte · 7df62a37
      Martyn Capewell authored
      7df62a37
    • Martyn Capewell's avatar
      Update code coverage results · 024d1cb3
      Martyn Capewell authored
      024d1cb3
    • Mai's avatar
      cpu-features: Update OS queryable hwcaps (#43) · bcb9ee3e
      Mai authored
      * cpu-features: Support hwcap for FEAT_MTE3
      * cpu-features: Support hwcap for FEAT_SME
      * cpu-aarch64: Allow specifying IDRegister field size
      This will be necessary for testing some SME extensions.
      
      Preserves existing behavior by defaulting the field size to 4 bits.
      
      * cpu-aarch64: Add skeleton for AA64SMFR0_EL1
      This register contains the bulk of the SME extension bitfields.
      
      * cpu-features: Support hwcap for FEAT_SME_I16I64
      * cpu-features: Support hwcap for FEAT_SME_F64F64
      * cpu-features: Support hwcap for FEAT_SME_I8I32
      * cpu-features: Support hwcap for FEAT_SME_F16F32
      * cpu-features: Support hwcap for FEAT_SME_B16F32
      * cpu-features: Support hwcap for FEAT_SME_F32F32
      * cpu-features: Support hwcap for FEAT_SME_FA64
      
      * cpu-aarch64: Handle hwcap auxvals separately
      HWCAP2 makes use of bit 31 and bit 32 which would fall outside the range
      of what can be handled by one array, so we can split the array into two
      arrays and combine over them individually.
      
      * cpu-features: Support hwcap for FEAT_WFxT
      * cpu-features: Support hwcap for FEAT_EBF16
      bcb9ee3e
  29. Aug 10, 2022
    • Martyn Capewell's avatar
      Add support for MOPS instructions · d6acdadc
      Martyn Capewell authored
      The MOPS extension to AArch64 adds support for instructions designed to
      accelerate functions like memcpy and memset. Implement these in the assembler,
      disassembler and simulator.
      d6acdadc
  30. Aug 04, 2022
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