Update README and supported instructions

See merge request !1

Update documentation to point to new repository and current list of supported
instructions.

Update the generated tests to remove hashes for vector lengths that are no
longer available and fix the generation tool for future tests.

NPOT SVE vector lengths are no longer allowed in AArch64, so remove the code
that handles them, add assertions, and update tests.

This makes it easier to work with containerised build environments.

Add an explicit yield() method to the assembler and macro-assembler, and use
them to test disassembly and simulation.

Fix format specifiers in the simulator to match the given arguments.
This will also silence -Wformat warnings when building with 32 bit
flags.

Use raw strings in lint.py to fix a Python error.

The DC ZVA instruction allows zeroing areas of memory, typically at block sizes
of 64 bytes per instance. Add support for this in all components, with tests.

Positional arguments to printf (eg. %1$s) are not allowed on Windows, so remove
uses of this in the disassembler, replacing them with an extension to the
existing NEONFormatDecoder class.

Patch prompted by https://github.com/Linaro/vixl/pull/122

Extend the SVE PMULL instructions to support Q destination elements when the
CPU feature is supported.

Most MOPS sequences implement one of options "A" or "B", with slightly
different flags in each case. Some `cpy` sequences also permit either
forward or backward iteration, with different register results.

This relies on a new overloaded form of `Equal64` that checks that a
register matches any one of the listed reference values.

In addition, renumber registers to avoid the use of `x16` in a couple of
tests, because this is a MacroAssembler scratch register and could cause
issues in the future.

Add support for two Neon SM4 accelerating instructions.

Some Neon instructions such as sqrdmulh only operate on H and S-sized elements.
The disassembler already restricts this, so extend checks to the simulator.
Additionally, reuse the new register/index extraction function in other parts of
the simulator.

Veneers were applied to backward branches too early, using only a quarter of the
range available for the branch. This was caused by confusion over the units the
range function expects; it accepts an offset in instructions.

Correct this and test veneers are applied only beyond the limit of the branch
range.

Previously, we would hit a VIXL_UNIMPLEMENTED, but this appears as a
test failure. Instead, use the "SKIPPED" marker, which is detected and
presented by `test.py`.

These encodings are "RESERVED".

The simulator will be updated in a subsequent commit, as part of a
refactoring of `VisitNEONScalar3Same` (to match the disassembler).

These instructions leave some bits of NZCV unmodified, so we need to
initialise them to make the behaviour consistent.

Collisions are unlikely, but there are enough PAuth tests that we
commonly see failures on hardware.

https://github.com/llvm/llvm-project/issues/108722

This is in order to prevent one instruction from appearing to refer to
two litersls.

Moving is permitted as it does not cause the same problem, and can be
useful to allow containers of Literal

Add a new document explaining the range limits of branches and literal-handling
instructions for AArch32 and AArch64, and the veneering capabilities of the
macro assembler.

Backwards (ie. bound) conditional branches that were out of range of the
immediate encoded in the instruction would fail, so apply a veneer to
these instruction by inverting the condition and using an unconditional branch.

Extend MTE irg test to check that all tags expected have been allocated.
Previously, the test wasn't detecting a case where the upper half of the range
was still unallocated.

Refactor assembler tests for fcvt by providing a helper function, extracting the
common cases, and moving the remainder to clearer input versus expected result
comparisons.

C++20's DR 2237 forbids using template-ids in constructors and
destructors, and GCC 14 started warning about this.

Add support for seven Neon SM3 accelerating instructions.