Notably:

- Make the simulator stack configurable, and make the guard regions
  functional.
- Fix simulation of frint and SVE while instructions.
- Add some missing mov aliases.

Change-Id: Icaa5c7fc597af007b32b023273483e09efcd91a1

The pointer to the buffer used for the ldapr tests could be potentially aligned
to the zero-initialised region, causing the test to fail. Fix this by
initialising the rest of the buffer to the correct value.

Change-Id: Ie0d63c58fc4dccdb8a0da1c3da1661875f208b1d

Change-Id: I63a4f52a716008e615a93bd30600d14dbb76bac0

The simulation of while was computing differences using 64-bit variables, which
didn't handle the overflow cases correctly for W-sized registers. Fix and add a
regression test.

Change-Id: I681f6ecb137d52830a58816fa34545342e6eb6bf

Change-Id: I5a237ee9225fd1c8f758498d72658ffbf1a90a61

Replace "dummy" with "placeholder".

Change-Id: I9af7f56c93b49c1a6428414601af1dec475ca3b8

Also fix the implementation of stack guards, and make these configurable
too.

Change-Id: Ic62ee326ed725616322ca8fa26d38b9a089d5043

This fixes a bug caused by an implicit conversion from `int64_t` to
`double`, as well as several related warnings (from recent versions of
Clang) in the "frint" tests.

Change-Id: Ie5dccbf7a86c5e3a608570bd0ffc566bf3813380

Logical immediate instructions using an immediate encoding that should be
reserved were being simulated. Prevent this by asserting the immediate is
valid.

Change-Id: Ic0388f3f941914d9fae92e0961c2ebf10c3a5d0b

The Halve function relied on shifting a signed value right. Replace with a
well-defined bitfield extraction.

Change-Id: I980d64ee92b68b5d4e213a2f338d810ec3999df7

Change-Id: I8461bc4c7b50d487334f3a022b614047f132ad61

Change-Id: Icaff12d06d4cee6852f16a419365b61a53dc1ffe

Provide an email contact address in the README for bug reports.

Change-Id: Iad9e8c2f135758da12597ab18fc8ea8d72006174

The assembler API provides prefetch functions that accept an enumeration for
the prefetch mode, but that relies on C++ undefined behaviour when used with
integer mode specifiers absent from the enumeration. This patch adds those
unallocated values.

Change-Id: I03fce9158deed2dda43ed35e5c6cbc93a4c3f9af

The regex didn't match when a prefix was used (i.e. through test.py).
Also, if `re.search()` failed, the whole process would hang. This patch
avoids that by explicitly catching a failed match.

Change-Id: Ib52f88c392c9b1d040aef55b60703dc66f11b824

Previously, the decoder applied a mask-and-value optimisation only if a decoding
table had two entries in it, with an explicit "otherwise" case. This patch makes
the optimisation also work when the case is implicit.

Change-Id: Iacbf96940e1c078fdcb4ad162f483b0d690b4108

The Arm ARM states dup-immediate with shift on byte-sized lanes is an undefined
encoding, so add assertions in the assembler to disallow this, and handle
the encoding appropriately in the disassembler and simulator.

Change-Id: Ibce08d2577e2b780dbb7e4fa478d2f8d18e99a39

Some tests assume rely on `sve_vl_in_bits()` to inform code generation.
We still generate SVE code on platforms without SVE, we just don't run
it, so we need to pick a valid (non-zero) default.

Change-Id: I25b457f63c54cccfc299128857244b2504127755

The macro assembler support for add/sub immediate could attempt to negate the
minimum int64_t value, which is undefined behaviour. Check the value before
negation.

Change-Id: If5c12515fbef490318a90930e7a362876b0e6dc5

Removed due to some cases showing worse performance.

Reverts:
960606b6
f3f5d246

Change-Id: I5b9585d112424d97e372bd264d084cb9caf92b5f

Making the constructor `constexpr` gives these "constant" rather than
"dynamic" initialisation, which guarantees that they'll be initialised
before any other dynamically-initialised static variables.

This makes it safe to make static variable initialisers dependent on the
result of `CPUFeatures::InferFromOS()` and similar functions.

Change-Id: Ib65e92273c7ac03d07e17cbe844b598ef3bc60ac

960606b6 removed a check for the encodability of a value within an add/sub
instruction, which allowed negation of min-int to pass through undetected.
This caused incorrect code generation, as the value wasn't inverted, but the
operation was.

Change-Id: I9c436a42a67aabca4873972c173ea104ef36f40e

Change-Id: I608c610da7de42328ed3984dabb56cf1401d7a15

Change-Id: I9afc03fb9e11546b9e6caf04497339bf45b285b6

After recent patches, we have exactly 64 CPU features. This patch makes
the mechanism flexible so that we can support more features in the
future.

Several operators on CPUFeatures had to be re-written as part of this,
so this patch replaces the default-argument implementations with a more
flexible template-based approach, which can accept more than four
features. Existing usage remains unaffected.

Change-Id: If91a3adb62669aa827464e857a90eb93a64db7a6

The `++` operators should return iterators, not values.

This also updates tests to match, and makes wider use of C++11
range-based `for` loops, where they simplify code.

Change-Id: I2c8ef422e851d6b16c8de2890ae16fc69817a738

For debugging purposes, it's useful to see what CPU features VIXL sees.

Change-Id: I6a501ee8c11e50252db713d7d295d84db0f2aee2

Change-Id: I3c893a6c1e3b25756999025a21ae310e5b3e199c

This adds support for all relevant features described in the latest
Armv8.6 XML.

Note that this removes the CPUFeatures::All() part of the
`API_CPUFeatures_format` test. It added little value to the test, and
was a burden to update when new features are added.

Change-Id: I276a0970be94c3adf2d0100874df0b82c7424a9b

Martyn Capewell authored Jul 01, 2020 and Jacob Bramley committed Jul 13, 2020

For immediates between 12 and 24 bits in size, a pair of add or sub instructions
can be used instead of mov, avoiding the need to allocate a temporary.

Change-Id: I114b4667dcc1bda094652e01d88069d012249dca

The value used for the second operand in indexed multiplies differs for each
segment (128-bit part) of a vector, but the simulator wasn't doing this for
FP multiplies. Fix and update the tests.

Change-Id: I9cc37ebef9d216243a23bedebea256826e1016cb

1. There was no test for 64-bit CASP.

2. The tests had some faulty code for obtaining aligned pointers. The
   natural alignment is sufficient anyway, so this patch removes the
   broken alignment code, and varies the addresses used to strengthen
   the test slightly.

   For the new CASP test, this patch uses the C++11 `alignas` specifier.

3. The simulation of CASP variants accessed memory in the wrong order.
   With this patch, the first-specified register in each pair accesses
   the lowest address.

4. We now check that `rs` and `rt` have the same format. Likewise for
   `rs2` and `rt2` in the CASP variants.

5. Register trace is improved: the `rs` (and `rs2`) update is traced as
   a memory read so we should suppress the log on the register write.
   This is what we do for normal loads.

Change-Id: I213c4b3de32305a8072fdc45357b67cbbf85ba9c

Martyn Capewell authored Jul 02, 2020 and Jacob Bramley committed Jul 06, 2020

Add assertions to the assembler to prevent the use of unsupported addressing
modes for prfb/h/w/d.

Change-Id: Ie12991eb2e29661eb266fc495e9164246371d10e

This is just a clean-up. We have the helper, so we should use it.

Change-Id: I8ee2c7929aef6ad737d7079eee62ffe3f7618857

We did this for PgLow8, but not for 4-bit 'pg' fields.

In practice, we plan to relax this in the future, permitting lane sizes
where they match the rest of the instruction, but this patch makes our
checks consistent in the meantime.

Change-Id: Ie791027f217eabab305dbd22b8c0e77926c9d3b8

The architecture disallows rm = x31/xzr for prefetch, so assert this in the
assembler.

Change-Id: I26e14688bde624d38eee40167fb3ada88acaaec7

FCMNE can return true when the comparison is unordered.

Change-Id: Ic1fa9a83cd9bde23faf2b13b69d3a7e9d1426a12

This matches conventions elsewhere in the API, and allows for immediate
synthesis. Immediate synthesis is not included in this patch.

Change-Id: If4bdc9cfd9d4bb83a9c015ef363291c1ff08a64a

This is generally useful, but in particular reduces scratch register
pressure in code sequences using ComputeAddress. For example:

    MemOperand addr(...);
    UseScratchRegisterScope temps(&masm);
    Register computed = temps.AcquireX();
    __ ComputeAddress(computed, addr);

Before this patch, that sequence usually required two scratch registers;
one for `computed`, and one for immediate synthesis inside
`ComputeAddress`. With this patch, the same code sequence only needs one
scratch register.

Change-Id: I9c93e6cab51bdacf36046d4d770dc81d1a65a34c

The `code_` field is a `uint8_t`, which is treated by stream formatters
as a `char`. This caused strange output from error messages in test
failure.

Change-Id: I16302e6bbd8977bb376d28c7b7cb2091f9891aba