- Fix some bugs.
- Revert an attempted optimisation that caused performance issues for
  some usage patterns.

Change-Id: I799e161005c0c9bae1b7a032f1680051bcfb6bbb

Some tests assume rely on `sve_vl_in_bits()` to inform code generation.
We still generate SVE code on platforms without SVE, we just don't run
it, so we need to pick a valid (non-zero) default.

Change-Id: I25b457f63c54cccfc299128857244b2504127755

The macro assembler support for add/sub immediate could attempt to negate the
minimum int64_t value, which is undefined behaviour. Check the value before
negation.

Change-Id: If5c12515fbef490318a90930e7a362876b0e6dc5

Removed due to some cases showing worse performance.

Reverts:
960606b6
f3f5d246

Change-Id: I5b9585d112424d97e372bd264d084cb9caf92b5f

Making the constructor `constexpr` gives these "constant" rather than
"dynamic" initialisation, which guarantees that they'll be initialised
before any other dynamically-initialised static variables.

This makes it safe to make static variable initialisers dependent on the
result of `CPUFeatures::InferFromOS()` and similar functions.

Change-Id: Ib65e92273c7ac03d07e17cbe844b598ef3bc60ac

960606b6 removed a check for the encodability of a value within an add/sub
instruction, which allowed negation of min-int to pass through undetected.
This caused incorrect code generation, as the value wasn't inverted, but the
operation was.

Change-Id: I9c436a42a67aabca4873972c173ea104ef36f40e

Change-Id: I608c610da7de42328ed3984dabb56cf1401d7a15

Change-Id: I9afc03fb9e11546b9e6caf04497339bf45b285b6

After recent patches, we have exactly 64 CPU features. This patch makes
the mechanism flexible so that we can support more features in the
future.

Several operators on CPUFeatures had to be re-written as part of this,
so this patch replaces the default-argument implementations with a more
flexible template-based approach, which can accept more than four
features. Existing usage remains unaffected.

Change-Id: If91a3adb62669aa827464e857a90eb93a64db7a6

The `++` operators should return iterators, not values.

This also updates tests to match, and makes wider use of C++11
range-based `for` loops, where they simplify code.

Change-Id: I2c8ef422e851d6b16c8de2890ae16fc69817a738

For debugging purposes, it's useful to see what CPU features VIXL sees.

Change-Id: I6a501ee8c11e50252db713d7d295d84db0f2aee2

Change-Id: I3c893a6c1e3b25756999025a21ae310e5b3e199c

This adds support for all relevant features described in the latest
Armv8.6 XML.

Note that this removes the CPUFeatures::All() part of the
`API_CPUFeatures_format` test. It added little value to the test, and
was a burden to update when new features are added.

Change-Id: I276a0970be94c3adf2d0100874df0b82c7424a9b

Martyn Capewell authored Jul 01, 2020 and Jacob Bramley committed Jul 13, 2020

For immediates between 12 and 24 bits in size, a pair of add or sub instructions
can be used instead of mov, avoiding the need to allocate a temporary.

Change-Id: I114b4667dcc1bda094652e01d88069d012249dca

The value used for the second operand in indexed multiplies differs for each
segment (128-bit part) of a vector, but the simulator wasn't doing this for
FP multiplies. Fix and update the tests.

Change-Id: I9cc37ebef9d216243a23bedebea256826e1016cb

1. There was no test for 64-bit CASP.

2. The tests had some faulty code for obtaining aligned pointers. The
   natural alignment is sufficient anyway, so this patch removes the
   broken alignment code, and varies the addresses used to strengthen
   the test slightly.

   For the new CASP test, this patch uses the C++11 `alignas` specifier.

3. The simulation of CASP variants accessed memory in the wrong order.
   With this patch, the first-specified register in each pair accesses
   the lowest address.

4. We now check that `rs` and `rt` have the same format. Likewise for
   `rs2` and `rt2` in the CASP variants.

5. Register trace is improved: the `rs` (and `rs2`) update is traced as
   a memory read so we should suppress the log on the register write.
   This is what we do for normal loads.

Change-Id: I213c4b3de32305a8072fdc45357b67cbbf85ba9c

Martyn Capewell authored Jul 02, 2020 and Jacob Bramley committed Jul 06, 2020

Add assertions to the assembler to prevent the use of unsupported addressing
modes for prfb/h/w/d.

Change-Id: Ie12991eb2e29661eb266fc495e9164246371d10e

This is just a clean-up. We have the helper, so we should use it.

Change-Id: I8ee2c7929aef6ad737d7079eee62ffe3f7618857

We did this for PgLow8, but not for 4-bit 'pg' fields.

In practice, we plan to relax this in the future, permitting lane sizes
where they match the rest of the instruction, but this patch makes our
checks consistent in the meantime.

Change-Id: Ie791027f217eabab305dbd22b8c0e77926c9d3b8

The architecture disallows rm = x31/xzr for prefetch, so assert this in the
assembler.

Change-Id: I26e14688bde624d38eee40167fb3ada88acaaec7

FCMNE can return true when the comparison is unordered.

Change-Id: Ic1fa9a83cd9bde23faf2b13b69d3a7e9d1426a12

This matches conventions elsewhere in the API, and allows for immediate
synthesis. Immediate synthesis is not included in this patch.

Change-Id: If4bdc9cfd9d4bb83a9c015ef363291c1ff08a64a

This is generally useful, but in particular reduces scratch register
pressure in code sequences using ComputeAddress. For example:

    MemOperand addr(...);
    UseScratchRegisterScope temps(&masm);
    Register computed = temps.AcquireX();
    __ ComputeAddress(computed, addr);

Before this patch, that sequence usually required two scratch registers;
one for `computed`, and one for immediate synthesis inside
`ComputeAddress`. With this patch, the same code sequence only needs one
scratch register.

Change-Id: I9c93e6cab51bdacf36046d4d770dc81d1a65a34c

The `code_` field is a `uint8_t`, which is treated by stream formatters
as a `char`. This caused strange output from error messages in test
failure.

Change-Id: I16302e6bbd8977bb376d28c7b7cb2091f9891aba

We tried to set the sign bit before multiplying, but this produced the
wrong result when the input is already negative.

Change-Id: I7b44070409ca265b1fae34792ebe43e5e53ce646

The `zn` value for the reference value for the `zd == zn == zm` case
must also be subject to `FPSegmentPatternHelper`.

Change-Id: Ic49b5e2500e9bb5fa46821cbe447bcdf891c813e

In this instruction, `pg` should be ignored when setting flags.

Also, simplify the test.

Change-Id: I9b8a73bdd0aaaebbecbccd1c446e17cd9d38ce8f

Change-Id: I18195d5f20ce8aaa9a5b89a91cb58bf8801852fc

The test checks that writes to RES0 fields are ignored. This is fragile,
because those fields are sometimes allocated as the architecture is
updated.

This patch updates the RES0 field specification, but also runs that part
of the test only on simulator builds.

Change-Id: Ia667e32519f9e2639f0e46f34426c9a51d21a0e0

Change-Id: I44f3cb4607ef593e1b54eed13fd5ad7ae7ef9cd6

In predicated operations, a lane size is required to use the governing predicate
correctly, and to reject instructions that don't support the lane size.

Consequently, this patch restores the lane size requirement on predicated
logical operations with predicate operands.

Change-Id: Ida32cc412a88c09454533dd8a5f12f46632d9750

Change 'tlss substitution to consider element size and memory size, which
simplifies the code in the visitors.

Change-Id: I0f34f206c6c68d0ddc6b4b115b982268f4dd89be

After implementation, these comments are not so useful, so remove the remaining
ones for consistency.

Change-Id: If47c5dffe13d27b92e8199b77dfbb2d5662e7327

This makes our SVE disassembly consistent with our NEON disassembly.

Change-Id: Iede57b6396e36913c879130101cdd487dbf63b8f

Change-Id: I3398f3fc3c737f3f4a4a15dce453dcfea0f5a670

Martyn Capewell authored Jun 23, 2020 and Jacob Bramley committed Jun 25, 2020

Introduce a ternary substitution placeholder in the disassembler, making some
addressing modes and merging/zeroing forms simpler.

Change-Id: I75d0c3cf40c73dd2e1ebce30c3753fd79368326d

Change-Id: If2ce450e490dd1ad4fcaba78985af84cc847986f

Make addressing mode modifiers MUL VL and LSL lower case to match the others.

Change-Id: I3388710128ac1dd4c3df503d4a5779e3ddf2936c

Include st1b, st1h, st1w and st1d.

Change-Id: I868c47a984723ea94ddc78f65f8c68680209c19c

Martyn Capewell authored May 12, 2020 and TatWai Chong committed Jun 22, 2020

Include st1b, st1h, st1w and st1d.

Change-Id: If7a5cd01ab8cc9dae813da81fc3cd9e34d9bc7b4