The SSDT table so far produced incorrect length fields in both the SSDT
table header and the scope. The scope length has so far been set for
the maximum size, and the surrounding table length has been clamped down
to a smaller size.

The SetPkgLength function should be passed the actual size of its
payload, and then needs to increase by the amount of bytes needed to
represent the length field.  In addition the TableSize adjustment
correction needs to consider the length of the scope opcode.

Signed-off-by: Patrick Wildt <patrick@blueri.se>
Acked-by: Ard Biesheuvel <ardb@kernel.org>

The number of entries specified in the typedef influences the length of
the whole structure, even though only one entry is filled.  This makes
some operating systems assume the second entry is also valid.  Reflect
reality by reducing the number of entries to a single one.

Signed-off-by: Patrick Wildt <patrick@blueri.se>
Acked-by: Ard Biesheuvel <ardb@kernel.org>

Setting the Always-on Capability bit in GTDT table for
system PE timers in sbsa platform.This is also required
for ACS sbsa level 3 test compliancy.

Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Ard Biesheuvel <ard.biesheuvel@arm.com>
Cc: Graeme Gregory <graeme@nuviainc.com>
Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>

[fixed compilation error]

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Tested-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Acked-by: Leif Lindholm <leif@nuviainc.com>

Compliant with BZ: #3665
https://bugzilla.tianocore.org/show_bug.cgi?id=3665



PcdPciMmio(32)64Translation PCD is relocated to MdePkg that leveraged
by both ARM and RISC-V arch. This patch uses the one from MdePkg
instead the one under ArmPkg.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Graeme Gregory <graeme@nuviainc.com>
Cc: Radoslaw Biernacki <rad@semihalf.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Acked-by: Leif Lindholm <leif@nuviainc.com>

Compliant with BZ: #3665
https://bugzilla.tianocore.org/show_bug.cgi?id=3665



PcdPciIoTranslation PCD is relocated to MdePkg that leveraged by
both ARM and RISC-V arch. This patch uses the one from MdePkg
instead the one under ArmVirtPkg.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Graeme Gregory <graeme@nuviainc.com>
Cc: Radoslaw Biernacki <rad@semihalf.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Acked-by: Leif Lindholm <leif@nuviainc.com>

The MADT GICC structure contains the field PhysicalBaseAddress, which
is needed for a GICv1/v2 implementation, or to indicate legacy
compatibility in modern GICs.

Linux commit 9739f6ef053f1, included in v5.12, adds a warning message
when this field is populated but invalid:
  [Firmware Bug]: CPU interface incapable of MMIO access

As it happens, we currently initialize this to PcdGicDistributorBase
instead of PcdGicInterruptInterfaceBase, and as a result we now trigger
this warning.

Since this is an SBSA reference implementation, and legacy GIC support
has never worked for this port, set the field to 0.

Signed-off-by: Leif Lindholm <leif@nuviainc.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Graeme Gregory <graeme@nuviainc.com>
Cc: Radoslaw Biernacki <rad@semihalf.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>

Set the DSDT revision value to 2 by using the define from Acpi60.h
EFI_ACPI_6_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION. This
causes the AML interpreter to use full 64-bit integers and math.

Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>

Commit 822634fc ("SbsaQemu: Update SbsaQemuAcpiDxe to use FdtHelperLib")
replaced the CountCpusFromFdt() function in SbsaQemuAcpiDxe with a call to
FdtHelperCountCpus() in FdtHelperLib. This ended up leaving static variables
FdtFirstCpuOffset and FdtCpuNodeSize uninitialised, such that the GetMpidr()
function kept returning the value for cpu 0.

Resolve this by moving the GetMpidr() function over to FdtHelperLib, where
it can again share these variables with FdtHelperCountCpus().

Fix up coding style issues as part of copy:
- Add m prefix to module-global variables.
- Add doxygen function comment header.

Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Graeme Gregory <graeme@nuviainc.com>
Cc: Radoslaw Biernacki <rad@semihalf.com>
Cc: Tanmay Jagdale <tanmay.jagdale@linaro.org>
Cc: Rebecca Cran <rebecca@nuviainc.com>
Reported-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Signed-off-by: Leif Lindholm <leif@nuviainc.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
Tested-By: Graeme Gregory <graeme@nuviainc.com>
Tested-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

Avoid re-using the NumCores variable as a loop index, in AddMadtTable:
add a new CoreIndex variable for that purpose.

Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>

o Add SMBIOS 3.4.0 tables using ArmPkg/Universal/Smbios.
o Bump the PcdSmbiosVersion PCD from 0x300 to 0x304 to indicate support
  for SMBIOS 3.4.0, as is required by SBBR.
o Add an implementation of OemMiscLib that provides the system
  information. The serial numbers, asset tags etc. are currently all
  fixed strings, to allow fwts to pass without errors.
o Add SMBIOS PCDs to identify the platform. The processor serial
  number, asset tag and part number are populated because otherwise
  fwts reports errors.

Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>

Use FdtHelperCountCpus from FdtHelperLib.

Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>

The CountCpusFromFdt function is now used in two places. Create
FdtHelperLib for this and similar functions.

Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>

The previous value of interrupt id used was not in sync
with the interrupt id being used in qemu sbsa-ref platform
due to a conflict before merging and was missed in last review.
This was preventing the watchdog interrupt from getting
identified.Updated SBSA-wdt interrupt id in Gtdt table
to rectify the issue.

Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Ard Biesheuvel <ard.biesheuvel@arm.com>
Cc: Graeme Gregory <graeme@nuviainc.com>
Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>

SBSA generic watchdog timer structure entry has been added
to GTDT table as per SBSAv6.0.
This enables acpi detection of wdt in qemu sbsa platform

Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Ard Biesheuvel <ard.biesheuvel@arm.com>
Cc: Graeme Gregory <graeme@nuviainc.com>
Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>
Reviewed-by: Graeme Gregory <graeme@nuviainc.com>
Acked-by: Leif Lindholm <leif@nuviainc.com>

The ACPI Tables providing library AcpiTables.inf uses
a lot of information that is available in the form of PCDs
for differnt platforms.

This patch replaces hardcoded values describing the PCIe,
AHCI, EHCI, and Serial with the appropriate PCDs.

Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Ard Biesheuvel <ard.biesheuvel@arm.com>
Cc: Tanmay Jagdale <tanmay.jagdale@linaro.org>
Signed-off-by: Tomas Pilar <tomas@nuviateam.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>

The ACPI tables require not only the base and the size
of various PCIe memory windows, but also the limit
defined as

Limit = Base + Size - 1

Given that ASL does not permit basic constant arithmetics when
defining resources or passing arguements to functions, we
define PCDs that hold these limits. The PCDs can then be modified
individually in platform DSC files.

Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Ard Biesheuvel <ard.biesheuvel@arm.com>
Cc: Tanmay Jagdale <tanmay.jagdale@linaro.org>
Signed-off-by: Tomas Pilar <tomas@nuviateam.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>

It is useful to have the PCDs of same type to be numbered
close together and thus a gap should be left between PCDs of
different types.

Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Ard Biesheuvel <ard.biesheuvel@arm.com>
Cc: Tanmay Jagdale <tanmay.jagdale@linaro.org>
Signed-off-by: Tomas Pilar <tomas@nuviateam.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>

The Qemu device tree for Sbsa platform now contains MPIDR value
for every CPU in the form of "reg" property under every CPU's
node. Hence, add a function that provides support to read this
value from the device tree.

Signed-off-by: Tanmay Jagdale <tanmay.jagdale@linaro.org>
Tested-by: Graeme Gregory <graeme@nuviainc.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>

1 - The SBSAQEMU_ACPI_ITOA contained a typo that put bogus characters
in the name if number of CPUs was greater than 10. It is safer to use
the AsciiSPrint function from PrintLib.

2 - The _UID fields were bogus, and indicated as bytes in AML instead of
a word. This caused extra Zeros to appear in disassembly. Fixed by
making them AML_WORD_PREFIX and putting CpuId in little endian.

3 - The table was a number of bytes too long, which causes bogus Zero in
dissassembly at end of table. Re-adjust code slightly to reduce table
size once we know the size of the length field.

Signed-off-by: Graeme Gregory <graeme@nuviainc.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>

Signed-off-by: Tanmay Jagdale <tanmay.jagdale@linaro.org>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>

Add support to create Processor Properties Topology Table at
runtime. The cache topology of each CPU is as follows:

                  CPU N
         ------------------------
         |  --------  --------  |
         |  | L1-I |  | L1-D |  |
         |  | 32KB |  | 32KB |  |
         |  --------  --------  |
         |  ------------------  |
         |  |    L2 512KB    |  |
         |  ------------------  |
         ------------------------

Signed-off-by: Tanmay Jagdale <tanmay.jagdale@linaro.org>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>

- Add support to create SSDT table at runtime. Since SSDT
  table is a data table, added a few helper macros to create
  the AML entries.
- Also added a function to calculate the length of Packages.

Signed-off-by: Tanmay Jagdale <tanmay.jagdale@linaro.org>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>

- Add support to create MADT table at runtime.
- Included a macro for GIC Redistributor structure initialisation.

Signed-off-by: Tanmay Jagdale <tanmay.jagdale@linaro.org>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>

- Add a new ACPI driver for the SbsaQemu platform which would
  handle any modifications needed for the ACPI tables.

- Add a parser function in this driver which parses the FDT created
  by Qemu to determine the number of CPUs and hence update the
  PcdCoreCount variable.

Signed-off-by: Tanmay Jagdale <tanmay.jagdale@linaro.org>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>

- Since the core count is dynamic and controlled by Qemu, move the
  PcdCoreCount from [PcdsFixedAtBuild] to [PcdsDynamic] section.

- Move FdtLib from [LibraryClasses.common.PEIM] to [LibraryClasses.common]
  section so that driver DXEs can use the device tree APIs.

Signed-off-by: Tanmay Jagdale <tanmay.jagdale@linaro.org>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>

Add PCI related entries to DSDT table along with the routing
entries. Also add the MCFG table.

Co-authored-by: Graeme Gregory <graeme.gregory@linaro.org>
Signed-off-by: Tanmay Jagdale <tanmay.jagdale@linaro.org>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>

- Add the following ACPI tables for SbsaQemu platform
    DSDT, FADT, GTDT, SPCR
- Created an Include directory to hold common header files.
- Also included the Acpiview shell utility.

Co-authored-by: Graeme Gregory <graeme.gregory@linaro.org>
Co-authored-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Signed-off-by: Tanmay Jagdale <tanmay.jagdale@linaro.org>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>

The EFI_FIMRWARE_VOLUME_HEADER is present at an offset in the
NOR flash of Sbsa QEMU model. Use the right RegionBaseAddress
so that the EFI firmware volume header can be found correctly.

Signed-off-by: Tanmay Jagdale <tanmay.jagdale@linaro.org>
Tested-by: Graeme Gregory <graeme.gregory@linaro.org>

The QEMU sbsa-ref platform provides an SBSA-compliant platform,
providing EL3/EL2 support, non-virtio interfaces, etc. This patch adds
initial support for this platform.

We are using FDF to compose EFI flash images with TF-A images.
Flash0 (secure) is used by BL1 and FIP (BL2 + BL31).
Flash1 contains EFI code and EFI variables.

Signed-off-by: Tanmay Jagdale <tanmay.jagdale@linaro.org>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>