- Dec 21, 2021
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Provide PcdLinuxBootFileGuid and use LinuxBootBootManager Library instance of the PlatformBootManager Library for linuxboot in RD-N2-Cfg1 platform. Signed-off-by:
Shriram K <shriram.k@arm.com>
Change-Id: Ic0127301237e7d10cb932ee506811bba169df77c -
Provide PcdLinuxBootFileGuid and use LinuxBootBootManager Library instance of the PlatformBootManager Library for linuxboot in RD-N2 platform. Signed-off-by:Shriram K <shriram.k@arm.com>
Change-Id: I76c89e0ca7ad5c744dc453dde88d0659d3515ba1 -
Provide PcdLinuxBootFileGuid and use LinuxBootBootManager Library instance of the PlatformBootManager Library for linuxboot in RD-V1 platform. Signed-off-by:Shriram K <shriram.k@arm.com>
Change-Id: Ia4a5ee6284e7f40e906b9a304f336ab6f1944f94 -
Change the FILE_GUID used in SgiPkgLinuxBoot.inf to a new GUID instead of UEFI Shell GUID. The commit 3122d76 used the UEFI Shell GUID for the stage-1 linuxboot kernel. The UEFI Shell GUID has been replaced with a new GUID since we are going to use LinuxBootBootManager Library instance which adds stage-1 linuxboot kernel as valid boot option. Hence, replacing the UEFI shell binary with the stage-1 linux kernel by using the UEFI Shell GUID in SgiPkgLinuxBoot.inf is no longer needed. Signed-off-by:Shriram K <shriram.k@arm.com>
Change-Id: If40d4087ab1566fbb947e287a10d3fbb765bbb9b -
Enable RD-N2-Cfg1 platform to choose linuxboot fdf file to replace the shell application with the stage-1 linuxboot kernel based on the build flag $LINUXBOOT_BUILD_ENABLED. This is an initial implementation of linuxboot for RD-N2-Cfg1 platform and not the final version. Signed-off-by:Shriram K <shriram.k@arm.com>
Change-Id: I607c2d6631a42115d50a801778933e4dc4e2c939 -
Enable RD-N2 platform to choose linuxboot fdf file to replace the shell application with the stage-1 linuxboot kernel based on the build flag $LINUXBOOT_BUILD_ENABLED. This is an initial implementation of linuxboot for RD-N2 platform and not the final verison. Signed-off-by:Shriram K <shriram.k@arm.com>
Change-Id: Ic56c0a9e1135c7a8ea19a210006772d7b23aa62a -
Enable RD-V1 platform to choose linuxboot fdf file to replace the shell application with the stage-1 linuxboot kernel based on the build flag $LINUXBOOT_BUILD_ENABLED. This is an initial implementation of linuxboot for RD-V1 platform and not the final version. Signed-off-by:Shriram K <shriram.k@arm.com>
Change-Id: I4091053ee4d3a216619556bf28fe20f2e070029f -
LinuxBoot is a firmware that replaces specific firmware functionality like the UEFI DXE phase with a Linux kernel and runtime. This patch adds LinuxBootPkg and SgiPlatformLinuxBoot.fdf which replaces the shell application with stage-1 linuxboot kernel and will be built when build flag $LINUXBOOT_BUILD_ENABLED is set. The stage-1 linuxboot kernel uses the same GUID as the shell application, enabling the user to boot the stage-1 linxuboot kernel when launching the Shell from the Boot Manager. This is an initial implementation of linuxboot for RD platforms and not the final version. Signed-off-by:Shriram K <shriram.k@arm.com>
Change-Id: I952bd76487c9a643e39cd82ddcb222417a883847 -
Extend the SMBIOS support for RD-N2-Cfg2 Platform. Change-Id: Ia2364214835eb23894b83d46533b65e2a3607acd Signed-off-by:
Pranav Madhu <pranav.madhu@arm.com> -
Add initial support for RD-N2-Cfg2 Platform. Signed-off-by:Aditya Angadi <aditya.angadi@arm.com> Change-Id: I09bb028c7ab839aa90732c336e1b22b7872679c8
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Add Madt, Dsdt, Iort, Mcfg, Srat and Ssdt ACPI tables that are specific for RD-N2-Cfg2 platform. Reuse the rest of the shared ACPI tables in SgiPkg. Signed-off-by: -
As a preparatory step towards adding support for RD-N2-Cfg2 Platfrom, add the Product ID lookup values for GetProductID API. Signed-off-by: -
OpenSSL requires floating point support. So remove nofp compiler flag from SgiPlatformMm dsc file. Signed-off-by:Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com> Change-Id: Iea343daf93d7a1e834fbeecd164a73be43232cc5
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The RD-N2-Cfg1 platform uses one instance of the IO Virtualization block to connect PL011 UART controllers and PL330 DMA controllers. Describe these devices by including the SsdtIoVirtBlk.asl ACPI table. In addition to this, add named-component IORT nodes for DMA PL330 DMA controllers that is interfaced with the SMMUv3 present in the IO virtualization block that is used to connect non-discoverable devices. This node maps to the DMA PL330 device node present in Ssdt table for the platform. Signed-off-by:
Vivek Gautam <vivek.gautam@arm.com> Signed-off-by:
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The RD-N2 platform uses one instance of the IO Virtualization block to connect PL011 UART controllers and PL330 DMA controllers. Describe these devices by including the SsdtIoVirtBlk.asl ACPI table. In addition to this, add named-component IORT nodes for DMA PL330 DMA controllers that is interfaced with the SMMUv3 present in the IO virtualization block that is used to connect non-discoverable devices. This node maps to the DMA PL330 device node present in Ssdt table for the platform. Signed-off-by:
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For platform that connect non-discoverable devices to IO virtualization block, add a SSDT table to describe those devices. PL011 UART controller and PL330 DMA controller are connected to the non-discoverable IO virtualization block. Signed-off-by:
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The IO virtualization block on reference design platforms allow connecting non-discoverable devices such as PL011 UART. On platforms that support this, initialize the UART controller connected to the IO virtualization block. Signed-off-by:Shriram K <shriram.k@arm.com>
Change-Id: I70bd3f790f51fa86707b0d300b3a70168731a4ff -
The IO topology on the RD-N2-Cfg1 platform is built using the IO Virtualization block. There are two instances of the IO Virtualization block on the RD-N2 platform and one of these instances is used to connect to a PCIe root bridge. Add RD-N2-Cfg1 platform specific IORT, MCFG and SSDT ACPI tables to represent this IO topology. Signed-off-by:
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The IO topology on the RD-N2 platform is built using the IO Virtualization block. There are five instances of the IO Virtualization block on the RD-N2 platform and four of these instances are used to connect to PCIe root bridge. Add RD-N2 platform specific IORT, MCFG and SSDT ACPI tables to represent this IO topology. Signed-off-by:
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Add helper macros for generation of the MCFG, SSDT and IORT ACPI table. The macro EFI_ACPI_SMMUv3_ID_TABLE_INIT simplifies the addition of the SMMUv3 ID remapping table in the IORT table. The macro EFI_ACPI_PCI_RC_ECAM_INIT describes the location of the PCI Express configuration space in the MCFG ACPI table. The macro EFI_ACPI_PCI_RC_INIT simplifies the addition of the root complex entry in the SSDT ACPI table. Signed-off-by:
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In preparation of adding multiple SMMU, IORT and PCIe root complex nodes into the IORT ACPI table, parameterize the existing IORT table. The SMMU interrupt numbers, device ID and base addresses are all parameterized using helper macros. PCDs for these parameters are defined and the platforms can define the value of these PCDs. Signed-off-by:
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For reference design platforms that support more than one PCIe host bridge, update the PCIe host bridge library implementation to allow support for upto four PCIe host bridges. PCDs are introduced to allow platforms to specify the values for bus count and the various MMIO base address and sizes. The available PCIe resources are split equally between the various host bridge instances in the system and macros have been introduced that makes it easier to implment this split. Signed-off-by:
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GicBase, GicVBase and GicHBase addresses are not used from GICv3 onwards in Madt table. Since RD-N2's GIC version is v4.1, make these base addresses as zero in Madt table. Signed-off-by: -
EINJ table is statically installed. If RAS is disabled EINJ table is not required. This change checks if RAS is enabled, if not then uninstalls the EINJ table from the platform. Signed-off-by:Omkar Anand Kulkarni <omkar.kulkarni@arm.com> Change-Id: Ib4babfcf06072522436674280bd1a6618d4c3b0c
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The error injection intructions that is pointed to by the EINJ table are placed in a region of memory reserved for it. Clear this memory region before it is used. Change-Id: I1aac512045372ac93cf1a5e2a8d670c5df7a523c Signed-off-by: -
DMC only supports SRAM error injection via integ_cfg registers. So these hacks added will catch the SRAM error injection events and convert them to DRAM errors, by programming appropriate DRAM error record registers. Signed-off-by: -
Current support for error injection is for DMC620 1-bit errors. Signed-off-by: -
Current support for error injection is for DMC620 1-bit errors. Signed-off-by: -
Enables firmware first error handling on the given platform. Installs and publishes the SDEI and HEST ACPI tables required for firmware first error handling. Signed-off-by: -
For ACPI tables that are generated dynamically, define the ACPI table header values that have to be used to build the table header. Co-authored-by:
Thomas Abraham <thomas.abraham@arm.com> Signed-off-by:
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Allow platforms to define the base address and size of the memory region that is reserved for MM drivers to populate the GHES generic error status block with information about the platform error. Co-authored-by:
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Enable the use of HEST table generation protocol, GHES error source descriptor protocol and DMC-620 MM driver on ARM Neoverse Reference Design platforms. This allows firmware-first error handling and reporting of DMC-620 memory controller's 1-bit DRAM ECC errors. Co-authored-by:
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DMC-620 memory controller improves system reliability by generating interrupts on detecting ECC errors on the data. Add a initial DMC-620 MM driver that implements a MMI handler for handling single-bit ECC error events originating from the DRAM. The driver implements the HEST error source descriptor protocol in order to publish the GHES error source descriptor for single-bit DRAM errors. The GHES error source descriptor that is published is of type 'memory error'. A GHES error source descriptor is published for each instances if the DMC-620 controller in the system. The driver registers a MMI handler for handling 1-bit DRAM ECC error events. The MMI handler, when invoked, reads the DMC-620 error record registers and populates the EFI_PLATFORM_MEMORY_ERROR_DATA type error section information structure with the corresponding information read from the error record registers. Co-authored-by:
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Thomas Abraham authored
Allow the use of ACPI system description table (SDT) protocol on Arm reference design platforms. This protocol will be used for dynamic addition of ACPI table such as the SDEI ACPI table. Signed-off-by:
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- Dec 20, 2021
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Jeremy Linton authored
First a huge thank you to Pete Batard for all the hard work landing the RPi code here, and keeping everyone in line. But, he has lots of commitments, and its time to give him a breather. As such, I will take over as a platform reviewer. Cc: Pete Batard <pete@akeo.ie> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Andrei Warkentin <awarkentin@vmware.com> Cc: Samer El-Haj-Mahmoud <Samer.El-Haj-Mahmoud@arm.com> Signed-off-by:
Jeremy Linton <jeremy.linton@arm.com> Acked-by:
Ard Biesheuvel <ardb@kernel.org> Reviewed-by:
Pete Batard <pete@akeo.ie> Acked-by:
Leif Lindholm <leif@nuviainc.com>
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- Dec 17, 2021
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Sami Mujawar authored
EbcDxe is not supported for AArch32 builds of the firmware. Therefore, move EbcDxe so that it is included only for AArch64 builds of the firmware. Signed-off-by:Sami Mujawar <sami.mujawar@arm.com>
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Sami Mujawar authored
ArmSoftFloatLib is required for the AARCH32 build of the firmware for SynQuacerEvalBoard. Therefore, add the missing ArmSoftFloatLib to SynQuacerEvalBoard.dsc Signed-off-by: -
Sami Mujawar authored
BdsDxe depends on VariablePolicyHelperLib, so move it out from VariableRuntimeDxe.inf and add it to LibraryClasses.DXE_DRIVER and LibraryClasses.DXE_RUNTIME_DRIVER. This is required to fix the build break in SynQuacerEvalBoard.dsc Signed-off-by:
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- Dec 16, 2021
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Nate DeSimone authored
Signed-off-by:Nate DeSimone <nathaniel.l.desimone@intel.com>
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Nate DeSimone authored
Signed-off-by:
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