Support for JunctionCity Platform
	- Add JunctionCity UBA's (Except GpioTable.c, IioBifurInit.c), all
	  other files in UBA folder are just name replacement (replaced TypeWilsonCity with TypeJunctionCity)
	- Disabled Intel ME IDE-R devices, KT devices to avoid BIOS POST time
	- Modified GetPlatformInfo() to check build time PcdBoardId and decide the board detection logic

Notes :
	V2 :
	- Moved Junction UBA folder from WhitleyOpenBoardPkg\Uba\UbaMain
	  to WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity
	- Modified WhitleyOpenBoardPkg/Platform/Pei/PlatformInfo/PlatformInfo.c GetPlatformInfo()
	  to check build time PcdBoardId and decide the board detection logic
	  which avoid maintaining the JunctionCity PEIM Copy
	- Include WhitleyOpenBoardPkg\PlatformPkg.dsc in JunctionCity PlatformPkg.dsc to avoid a lot of duplicate code
	- Fix typo errors and unwanted statements in ReadMe.md
	- Fix coding style errors.

Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Harikrishna Doppalapudi <harikrishnad@ami.com>
Cc: Manish Jha <manishj@ami.com>
Cc: Sureshkumar Ponnusamy <sureshkumarp@ami.com>
Cc: Manickavasakam Karpagavinayagam <manickavasakamk@ami.com>
Cc: Zachary Bobroff <zacharyb@ami.com>

Signed-off-by: Manickavasakam Karpagavinayagam <manickavasakamk@ami.com>
Reviewed-by: Isaac Oram <isaac.w.oram@intel.com>

The SSDT table so far produced incorrect length fields in both the SSDT
table header and the scope. The scope length has so far been set for
the maximum size, and the surrounding table length has been clamped down
to a smaller size.

The SetPkgLength function should be passed the actual size of its
payload, and then needs to increase by the amount of bytes needed to
represent the length field.  In addition the TableSize adjustment
correction needs to consider the length of the scope opcode.

Signed-off-by: Patrick Wildt <patrick@blueri.se>
Acked-by: Ard Biesheuvel <ardb@kernel.org>

The number of entries specified in the typedef influences the length of
the whole structure, even though only one entry is filled.  This makes
some operating systems assume the second entry is also valid.  Reflect
reality by reducing the number of entries to a single one.

Signed-off-by: Patrick Wildt <patrick@blueri.se>
Acked-by: Ard Biesheuvel <ardb@kernel.org>

This commit adds the SMBIOS type 17 table support for Developerbox.
The SPD can be accessed only from the SCP through I2C bus,
so this commit expects that SCP-firmware reads the SPD and
stores it in the non-secure SRAM.

This commit also reduces the edk2 stack size to allocate
the space for storing SPD. It requires 2KB, 512bytes * 4 DIMMs.

Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Masami Hiramatsu <masami.hiramatsu@linaro.org>
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3717



V2 of the PCH SPI PPI and PCH SPI Protocol were recently added to
IntelSiliconPkg. This change removes the v1 definitions.

V2 is intended to better support multiple silicon generations which
aligns with the goals of IntelSiliconPkg.

Cc: Ray Ni <ray.ni@intel.com>
Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
Reviewed-by: Sai Chaganty <rangasai.v.chaganty@intel.com>

SynQuacerI2cDxe.c (and no other Socionext source files) has LF instead of
CRLF line endings, so fix that.

Signed-off-by: Leif Lindholm <leif@nuviainc.com>
Cc: Masami Hiramatsu <masami.hiramatsu@linaro.org>
Acked-by: Ard BIesheuvel <ardb@kernel.org>
Acked-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>

The idea came from DeviceManagerUiLib that all related menu settings can
be placed under a common entry. This change intends to provide a central
point for all platform menus by creating a Platform Manager entry located
under Device Manager entry of UiApp.

New classuuid called gPlatformManagerFormsetGuid was introduced for
platform menus which want to be reached through this Platform Manager.

Cc: Thang Nguyen <thang@os.amperecomputing.com>
Cc: Chuong Tran <chuong@os.amperecomputing.com>
Cc: Phong Vo <phong@os.amperecomputing.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>

Signed-off-by: Nhi Pham <nhi@os.amperecomputing.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>

This change supports storing the UEFI non-volatile varibles on the
Flash through below modules:
* FlashPei driver helps to restore the saved variables from
  flash on each boot.
* FlashFvbDxe driver provides the implementation for the
  gEfiFirmwareVolumeBlock protocol

Cc: Thang Nguyen <thang@os.amperecomputing.com>
Cc: Chuong Tran <chuong@os.amperecomputing.com>
Cc: Phong Vo <phong@os.amperecomputing.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>

Signed-off-by: Nhi Pham <nhi@os.amperecomputing.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>

BootProgress will send 32-bit UEFI Status Code via doorbell to report
its progress status.
Currently support reporting Progress Status Code and Error Status Code
only. Other types of Status Code are ignored.

Cc: Thang Nguyen <thang@os.amperecomputing.com>
Cc: Chuong Tran <chuong@os.amperecomputing.com>
Cc: Phong Vo <phong@os.amperecomputing.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>

Signed-off-by: Nhi Pham <nhi@os.amperecomputing.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>

This library adds the support for retrieving and updating system
datetime over real RTC PCF85063 device on Mt. Jade platform instead of
using virtual RTC.

Cc: Thang Nguyen <thang@os.amperecomputing.com>
Cc: Chuong Tran <chuong@os.amperecomputing.com>
Cc: Phong Vo <phong@os.amperecomputing.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>

Signed-off-by: Nhi Pham <nhi@os.amperecomputing.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>

The DwGpioLib library provides basic functions to control the GPIO
controller on Ampere Altra processor.

Cc: Thang Nguyen <thang@os.amperecomputing.com>
Cc: Chuong Tran <chuong@os.amperecomputing.com>
Cc: Phong Vo <phong@os.amperecomputing.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>

Signed-off-by: Nhi Pham <nhi@os.amperecomputing.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>

The DwI2cLib library provides basic functions to control the I2C
controller on Ampere Altra processor.

Cc: Thang Nguyen <thang@os.amperecomputing.com>
Cc: Chuong Tran <chuong@os.amperecomputing.com>
Cc: Phong Vo <phong@os.amperecomputing.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>

Signed-off-by: Nhi Pham <nhi@os.amperecomputing.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>

Provides functions to access the NVRAM, NVRAM2 and FailSafe region on the
Flash over MM communication.

Cc: Thang Nguyen <thang@os.amperecomputing.com>
Cc: Chuong Tran <chuong@os.amperecomputing.com>
Cc: Phong Vo <phong@os.amperecomputing.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>

Signed-off-by: Nhi Pham <nhi@os.amperecomputing.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>

This commit adds the support for Ampere’s Altra processor-based Mt. Jade
platform that provides up to 160 processor cores in a dual socket
configuration. The essential modules are wired up enough to boot system
to EDK2 UiApp.

Cc: Thang Nguyen <thang@os.amperecomputing.com>
Cc: Chuong Tran <chuong@os.amperecomputing.com>
Cc: Phong Vo <phong@os.amperecomputing.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>

Signed-off-by: Nhi Pham <nhi@os.amperecomputing.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>

Add PCI CpuIo protocol to RISC-V.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>

Use mtime CSR library interface to access mtime
CSR.

Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>

Create library instances of reading Machine mode timer.
- MacineModeTimerLib is used to read mtime CSR through
  platfrom library.
- EmulatedMacineModeTimerLib is used to read mtime CSR
  through shadow CSR.

Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>

Update opensbi library to a731c7e36988c3308e1978ecde491f2f6182d490,
which is based on v0.9.

Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
Signed-off-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>

This is the library instance to provide platform_override for the
special RISC-V platform. This module incorporates with
OpensbiPlatformLib and RISC-V Opensbi library.

Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>

CoreInfoHob uses RiscVFirmwareContextLib to get the
pointer of FirmwareContext.

Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>

1. Use RISC-V PeiCoreEntryPoint library instance for opensbi
   to switch to the next phase with arg0 as HART Id and arg1
   as the SEC to PEI handoff data.
2. Introduce EDK2 opensbi platform operation functions.
   With this, OEM can has its won platform initialization code
   before and/or after opensbi vendor platform functions.

Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>

khasim-mohammed authored Nov 05, 2021 and Sami Mujawar committed Nov 08, 2021

This patch introduces new PCDs required to enable
chip to chip interface and corresponding memory map is updated.

Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@arm.com>
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@Arm.com>

khasim-mohammed authored Nov 05, 2021 and Sami Mujawar committed Nov 08, 2021

This patch adds missing documentation for few of the functions
and fixes few formatting changes.

Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@arm.com>
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>

Some system may has multi PCI root bridges. It needs to use PciRootBridgeIo
 protocol to get the root bridge count. Scan each root bridge to get all
 PCI devices.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3695



Signed-off-by: Robert Kowalewski <robert.kowalewski@intel.com>
Signed-off-by: Sheng Wei <w.sheng@intel.com>
Cc: Jenny Huang <jenny.huang@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
Cc: Robert Kowalewski <robert.kowalewski@intel.com>
Cc: Albecki Mateusz <mateusz.albecki@intel.com>
Cc: Kolakowski Jacek <Jacek.Kolakowski@intel.com>
Reviewed-by: Jenny Huang <jenny.huang@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3307



Updates references to the "PCH_SPI_PROTOCOL" to instead refer to
"PCH_SPI2_PROTOCOL".

Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Heng Luo <heng.luo@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
Reviewed-by: Heng Luo <heng.luo@intel.com>

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3307



Updates the library to identify flash regions by GUID and internally
map the GUID entries to values specific to TigerlakeSiliconPkg.

Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Heng Luo <heng.luo@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3307



Updates references to the "PCH_SPI_PROTOCOL" to instead refer to
"PCH_SPI2_PROTOCOL".

Cc: Agyeman Prince <prince.agyeman@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3307



Updates the library to identify flash regions by GUID and internally
map the GUID entries to values specific to SimicsIch10Pkg.

Cc: Agyeman Prince <prince.agyeman@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3307



Updates references to the "PCH_SPI_PROTOCOL" and "PCH_SPI_PPI" to
instead refer to "PCH_SPI2_PROTOCOL" and "PCH_SPI2_PPI".

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3307



Updates the code to identify flash regions by GUID and internally
map the GUID entries to values specific to KabylakeSiliconPkg.

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3307



Updates references to the "PCH_SPI_PROTOCOL" and "PCH_SPI_PPI" to
instead refer to "PCH_SPI2_PROTOCOL" and "PCH_SPI2_PPI".

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3307



Updates the library to identify flash regions by GUID and internally
map the GUID entries to values specific to CoffeelakeSiliconPkg.

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3307



Adds a new SPI 2 protocol (and corresponding PPI) that identify
flash regions by GUID instead of fixed values defined in an enum.

Packages consuming IntelSiliconPkg are able to associate a given
GUID with their chosen values based on their SPI flash details as
implemented in their PCH_SPI2_PROTOCOL instance.

Cc: Ray Ni <ray.ni@intel.com>
Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Sai Chaganty <rangasai.v.chaganty@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3307



This change identifies flash regions by GUID instead of fixed values
since the flash region identifiers are now defined in IntelSiliconPkg
and different boards may want to associate a flash region identifier
with a board/platform specific value.

The flash region GUIDs are intended to provide identifier consistency
across board implementations improving portability of the code among
IntelSiliconPkg consumers.

Cc: Ray Ni <ray.ni@intel.com>
Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Sai Chaganty <rangasai.v.chaganty@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3307



The following PPI and Protocols have moved to IntelSiliconPkg. The
remaining definitions in TigerlakeSiliconPkg are removed and libs/
modules that need to reference IntelSiliconPkg are updated.

 1. gPchSpiProtocolGuid
 2. gPchSmmSpiProtocolGuid
 3. gPchSpiPpiGuid

Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Heng Luo <heng.luo@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3307



gEfiSmmSpiProtocolGuid is now declared in IntelSiliconPkg.dec. This
change updates Ich10Pkg to remove the protocol declaration in the
package and update libraries and modules to use the protocol from
IntelSiliconPkg.

Cc: Agyeman Prince <prince.agyeman@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3307



The following PPI and Protocols have moved to IntelSiliconPkg. The
remaining definitions in KabylakeSiliconPkg are removed and libs
modules that need to reference IntelSiliconPkg are updated.

 1. gPchSpiProtocolGuid
 2. gPchSmmSpiProtocolGuid
 3. gPchSpiPpiGuid

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3307



The following PPI and Protocols have moved to IntelSiliconPkg. The
remaining definitions in CoffeelakeSiliconPkg are removed and libs/
modules that need to reference IntelSiliconPkg are updated.

 1. gPchSpiProtocolGuid
 2. gPchSmmSpiProtocolGuid
 3. gPchSpiPpiGuid

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3307



The library has been consolidated with instances in other Intel
silicon packages as a single instance in IntelSiliconPkg

Cc: Agyeman Prince <prince.agyeman@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3307



The library has been consolidated with instances in other Intel
silicon packages as a single instance in IntelSiliconPkg

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>