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    • Thomas Abraham's avatar
      rdfremont: configure system counter implementation defined registers · 39858a0e
      Thomas Abraham authored
      
      
      On RD-Fremont and variant platforms, the system counter should increment
      at 1GHz as per SBSA requirement. With the refclk at 125Mhz, these
      platforms require a per-tick system counter increment of 8. This
      increment value has to be programmed in the implementation defined
      registers of system counter control register frame. So provide the table
      of impdef register offsets and its corresponding values in the gtimer
      module config data.
      
      It is SCP firmware that configures the system counter register frame and
      so the table is supplied as config data to only the SCP firmware. For
      the MCP firmware, update the system counter increment frequency as 1GHz.
      
      Signed-off-by: Thomas Abraham's avatarThomas Abraham <thomas.abraham@arm.com>
      Change-Id: Ibda329735f9ac9df61434b2b5aafabd69da956da
      39858a0e
    • Thomas Abraham's avatar
      rdfremont: reorganize common definitions · 69b8cc1e
      Thomas Abraham authored
      
      
      The refclk speed is a common definition for SCP, MCP and LCP. So remove
      SCP and MCP specific definitions of refclk speed and consolidate it
      under a common css definitions file. In addition to this, add the
      per-tick system counter increment value definition that is required to
      comply with the SBSA requirement of system counter incrementing at 1GHz.
      
      Signed-off-by: Thomas Abraham's avatarThomas Abraham <thomas.abraham@arm.com>
      Change-Id: Iebe89ddf1cd07468baefcfed432d58044e476487
      69b8cc1e
    • Thomas Abraham's avatar
      rdn2: remove incorrect configuration of system counter increment value · 070b776c
      Thomas Abraham authored
      
      
      On the RD-N2 config-3 platform, the system counter per-tick increment
      value is configured after the system counter has been enabled. This is
      incorrect as the system counter has to count at 1GHz from the start when
      enabled. So remove this incorrect configuration of the system counter
      per-tick increment value register.
      
      Now that the module 'syscnt_impdef' is enabled for all RD-N2 platform
      and variants, that is sufficient to ensure that the per-tick increment
      value is configured before the system counter is started.
      
      Signed-off-by: Thomas Abraham's avatarThomas Abraham <thomas.abraham@arm.com>
      Change-Id: Ic9cede5a1b972f3570200557ec5f65aee70d5138
      070b776c
    • Thomas Abraham's avatar
      rdn2: configure system counter implementation defined registers · d5083716
      Thomas Abraham authored
      
      
      On RD-N2 and variant platforms, the system counter should increment at
      1GHz as per SBSA requirement. With the refclk at 125Mhz, these platforms
      require a per-tick system counter increment of 8. This increment value
      has to be programmed in the implementation defined registers of system
      counter control register frame. So provide the table of impdef register
      offsets and its corresponding values in the gtimer module config data.
      
      It is SCP firmware that configures the system counter register frame and
      so the table is supplied as config data to only the SCP firmware. For
      the MCP firmware, update the system counter increment frequency as 1GHz.
      
      Signed-off-by: Thomas Abraham's avatarThomas Abraham <thomas.abraham@arm.com>
      Change-Id: I1a1a1562d7dbd5a06ec6adcca1a6e9c1f75f878b
      d5083716
    • Thomas Abraham's avatar
      neoverse-rd: define system counter impdef registers · d997fcb7
      Thomas Abraham authored
      
      
      The system counter implementation specific registers are similar for
      RD-N2 and RD-Fremont platforms. So add common file that defines the
      impdef register offsets in the system counter register frame.
      
      Signed-off-by: Thomas Abraham's avatarThomas Abraham <thomas.abraham@arm.com>
      Change-Id: I5424f5d36c3099ec3f8a7876cdb697c3affeac8c
      d997fcb7
    • Thomas Abraham's avatar
      rdn2: fix refclk clock speed · e083ee6a
      Thomas Abraham authored
      
      
      The refclk clock speed is incorrectly set to 100MHz for RD-N2 platform
      configs 0, 1 and 2. It should be 125MHz instead of 100MHz. Fix this
      accordingly.
      
      Signed-off-by: Thomas Abraham's avatarThomas Abraham <thomas.abraham@arm.com>
      Change-Id: I357feb55142f7ab332646aafbfef553cd40c7e1e
      e083ee6a
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