Simplify the cache management by removing most of the logic from the
driver itself to user overridable weak functions for cache flush/clean
and invalidation.

The driver now calls the cache flush/clean before each NPU command
stream with a full list of base pointers/base addresses and their size.
This allows full freedom to implement any desired logic for cache
coherence management outside of the driver. This changes the function
prototype for the flush and invalidate functions.

As there's no longer a need to keep a bitmask of which base
pointers/addresses to flush/clean/invalidate, those functions have been
removed.

To guarantee that the driver works in all cases and doesn't get affected
by potential speculative loads, the cache invalidation call has been
moved to after the NPU has finished.

Due to the backwards incompatible changes to the function prototypes,
the driver version has been bumped to 1.0.0

Change-Id: Ibfd755876842edc911fecebf34fa80c22f287ca4
Signed-off-by: Jonny Svärd <jonny.svaerd@arm.com>

Several repos have moved from ML Platform to GitLab, change all
references to use the new location.

Signed-off-by: Jonny Svärd <jonny.svaerd@arm.com>
Change-Id: Ie0a1023c1fd80de9622bf61992cde6846b9d674e

Update the README document with details of various compiler flags used
to make it easier for the user to find them.

Change-Id: I96a565b1384e211c4e68f0f11e1578261b6c1925
Signed-off-by: Rajasekaran Kalidoss <rajasekaran.kalidoss@arm.com>

Add comments about ethosu_flush_dcache() being deprecated and not
recommended to be implemented. Cache coherency for regions that are
shared by the CPU and NPU are to be handled by the application before an
inference is invoked, as the driver will otherwise do it for every
invokation hurting performance.

Remove cache flush/clean and invalidation calls for all base pointers
and instead add a cache flush/clean and invalidation base pointer mask.
This mask defaults to only mark the scratch base pointer (tensor arena)
for both flush/clean and invalidation. The scratch base pointer is the
only one containg RW data shared between the CPU and NPU.

For the typical case, cache invalidation is only required to be done on
the scratch/tensor arena base pointer, as that contains the OFM data.
All other base pointers are either read only or in the case of dedicated
sram mode being used, the fast memory is only meant to be used by the
NPU and thus no cache coherency issues exist.

Add a helper function to allow the cache masks to be modified for
advanced use cases. The cache mask for flush and invalidate are both 8
bit masks where bit 0 corresponds to base pointer 0, bit 1 corresponds
to base pointer 1 etc.

Update previously incorrect documentation that the addresses shipped to
cache functions needs to be 16 byte aligned, they need to be 32 byte
aligned (or the cache line size of the CPU).

Invalidation of the complete cache is no longer supported as this is
potentially dangerous, especially in async use cases where the CPU might
be doing other things while the NPU is running. base_addr_size is now
required to be set for all invoke calls, or an assert will trigger.

Change-Id: Ica665ebfb84329ec5e56c224859516036fc08d2c
Signed-off-by: Jonny Svärd <jonny.svaerd@arm.com>

Introduce ETHOSU_INFERENCE_TIMEOUT CMake variable to set an
arbitrary timeout value that will be sent as argument to
ethosu_semaphore_take() for the interrupt semaphore. Adding
the ability to have a timeout for an inference. (Defaults to
no timeout/wait forever.)

Implement a placeholder mutex for the baremetal example and add
error checks for mutex_create() call.

Change-Id: Ia74391620340a27c23dc3d15f9ba742c674c8bfa
Signed-off-by: Jonny Svärd <jonny.svaerd@arm.com>

Change-Id: I68660361c7af062ac76a38f86c118ddc74e1c0d6

Jonny Svärd authored May 24, 2022 and Kristofer Jonsson committed May 25, 2022

Currently TARGET_CPU should be used to set CPU+features, if
using core_platform provided toolchain files.

Change-Id: I053cc25de12501a2773238820daa150f9ea20fa7

- Improve build section by describing new build options
- Add a section about driver APIs and basic usage examples
- Add a section about mutexes and semaphores
- Add a section about begin/end inference callbacks
- Add a brief section about driver implementation design
- Fix markdown title/subtitles structure
- Small fixing of typos and rewording

Also add .gitignore

Change-Id: I7216a2b72b0dfaa605620f4344da205235339ddb

Updating readme files with trademark information.

Change-Id: Id5313510777b771231f42701faff1da93765deda

Implement a weak linked function to handle the data cache.
If the specific device is implementing a data cache the function should
be overriden with device specific implementation of the flush/invalidate
functions to make sure that the cache is properly maintained with
regards to the NPU DMA transaction.

Change-Id: I175644ef37bee62cc77d789d2b7bc3073e72ea5a

Change-Id: Id96dd7824352992c07b5fa3ce8a39a84926557a8

Add information how to contribute and how to report security incidents.

Change-Id: I7946e66b30c4e338ffa5a279b5d769a764c34f0f

Change-Id: I3cdf8f21ed58ace2f2c739748d788ec97fb4083a