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  1. Nov 15, 2019
  2. Nov 13, 2019
  3. Nov 12, 2019
    • Nicola Mazzucato's avatar
      mock_sensor: Add module · 2ee5313b
      Nicola Mazzucato authored
      
      
      This patch adds a mocker for sensors.
      This module implements the sensor driver API and
      defers the get_value requests. This module requires
      the timer facilities in order to setup an alarm.
      This would emulate a sensor that provides a value
      through an ISR and a call to the driver_response API
      of the sensor module.
      
      This module can be used to test sensor call flow
      in platforms that do not provide asynchronous sensor
      drivers.
      
      Change-Id: I37baa428c12d6aa1c3de2f6f534ab5ac158f2352
      Signed-off-by: Nicola Mazzucato's avatarNicola Mazzucato <nicola.mazzucato@arm.com>
      2ee5313b
  4. Nov 11, 2019
  5. Nov 08, 2019
  6. Nov 07, 2019
  7. Nov 06, 2019
    • Chris Kay's avatar
      sgm775: Add `psu` element index abstractions · a5b023b2
      Chris Kay authored
      
      
      This commit adds enumerations representing the indices of SGM-775's
      `psu` and `mock_psu` elements, in order to avoid tying them to a
      particular integer literal when we need to refer to an element.
      
      Change-Id: I3f6aec07524b29ceb610dc05096eba8b5206ca25
      Signed-off-by: Chris Kay's avatarChris Kay <chris.kay@arm.com>
      a5b023b2
    • Chris Kay's avatar
      sgm775: Add `timer` element index abstractions · 98877706
      Chris Kay authored
      
      
      This commit adds an enumeration representing the indices of SGM-775's
      `timer` elements, in order to avoid tying them to a particular integer
      literal when we need to refer to an element.
      
      Change-Id: Ic68cb4f1d9f1404f6b97dbc14de7f25fa2c2b0eb
      Signed-off-by: Chris Kay's avatarChris Kay <chris.kay@arm.com>
      98877706
    • Chris Kay's avatar
      mock_psu: Add asynchronous driver support · 78d25331
      Chris Kay authored
      
      
      This commit allows elements of the `mock_psu` module to emulate
      asynchronous operations.
      
      Enabling asynchronous operations forces requests to the element to be
      pended for later completion, and is useful for testing interfaces that
      interact with `mock_psu` which need to support this functionality.
      
      Change-Id: Ic52221c510de8da60501a163b3f7dcacef6b0a3b
      Signed-off-by: Chris Kay's avatarChris Kay <chris.kay@arm.com>
      78d25331
    • Chris Kay's avatar
      psu: Add support for asynchronous drivers · b5188d76
      Chris Kay authored
      
      
      This commit adds the extra handling required to support drivers that may
      pend certain requests, as opposed to acting on them immediately.
      
      This extra support is intended for drivers that might otherwise busy-
      wait for extended periods, such as when they do not immediately know the
      result of an operation they have begun.
      
      Change-Id: I39aa9e4129d833044bd0e87b324c701d59a6908f
      Signed-off-by: Chris Kay's avatarChris Kay <chris.kay@arm.com>
      b5188d76
    • Etienne Carriere's avatar
      fwk_interrupt: add missing declaration of exported functions · 5fe32fc4
      Etienne Carriere authored
      
      
      Add missing declaration of exported functions fwk_interrupt_init()
      and fwk_interrupt_set_isr_fault().
      
      fwk_interrupt_init() is an effective exported API hence declared from
      fwk_interrupt.h.
      
      fwk_interrupt_set_isr_fault() is a test only API hence declared from
      internal/fwk_interrupt.h.
      
      Signed-off-by: default avatarEtienne Carriere <etienne.carriere@linaro.org>
      5fe32fc4
  8. Nov 04, 2019
    • Manoj Kumar's avatar
      n1sdp: increase pcie inbound register size to 48-bits · 888c4125
      Manoj Kumar authored
      
      
      This patch increases the PCIe RP inbound region size to 48-bits
      as there are cases where endpoint can generate a 48-bit VA
      which gets translated by SMMU.
      
      Change-Id: Ieca1c59b99f5da50e141237cd79f12ed17fc6ed7
      Signed-off-by: Manoj Kumar's avatarManoj Kumar <manoj.kumar3@arm.com>
      888c4125
    • Manoj Kumar's avatar
      n1sdp: fix power domain tree view based on chip ID · 51fc9874
      Manoj Kumar authored
      
      
      This patch fixes the power domain tree view for master and slave
      chips differently.
      
      Master chip sees the power domains of both master and slave chips
      whereas slave sees the power domain of only slave chip.
      
      Master chip's SCP PD tree view will look like:
      
                          -----SYSTOP (LOGICAL)-------
                         /                            \
                        /                              \
                  ---SYSTOP0--                   ---SYSTOP1--
                 /      |     \                 /      |     \
                /       |      \               /       |      \
               /        |       \             /        |       \
          CLUS0       CLUS1    DBGTOP0   CLUS2       CLUS3     DBGTOP1
         /    \      /    \             /    \      /    \
       CPU0--CPU1--CPU2--CPU3---------CPU4--CPU5--CPU6--CPU7
      
       Here the SYSTOP LOGICAL is at PD level 3 but currently there is an
       issue  in handling level 3 in PD driver. So until it is fixed, the
       master chip's SCP uses the following PD tree view:
      
                  --------------SYSTOP0--------------
                 /        /        |         \       \
                /        /         |          \       \
               /        /          |           \       \
          CLUS0       CLUS1      CLUS2       CLUS3  DBGTOP0
         /    \      /    \      /    \      /    \
       CPU0--CPU1--CPU2--CPU3--CPU4--CPU5--CPU6--CPU7
      
       The slave chip's SCP however looks a single chip view of PD tree having
       its own local power domains and looks like below:
      
                  ---SYSTOP0--
                 /      |     \
                /       |      \
               /        |       \
          CLUS0       CLUS1    DBGTOP0
         /    \      /    \
       CPU0--CPU1--CPU2--CPU3
      
      Change-Id: I83b339261d6ddda9660d5d8c6b575fadf48e70bd
      Signed-off-by: Manoj Kumar's avatarManoj Kumar <manoj.kumar3@arm.com>
      51fc9874
    • Manoj Kumar's avatar
      n1sdp: add config for remote pd driver and include in build · a54d8fd0
      Manoj Kumar authored
      
      
      Change-Id: I079a4966ef6674dad5886314883f1b20fce61342
      Signed-off-by: Manoj Kumar's avatarManoj Kumar <manoj.kumar3@arm.com>
      a54d8fd0
    • Manoj Kumar's avatar
      n1sdp_remote_pd: add remote PD driver to handle slave domains · 6fd84614
      Manoj Kumar authored
      
      
      This patch adds remote power domain driver to handle the slave
      power domains from master.
      
      In multichip scenario, the power domain tree view of master and slave
      are different. Master sees the power domain of both local domains
      and slave chips' domains. However slave sees only it own local
      power domains.
      
      In master chip, the power domain handling of local domains is managed
      through ppu_v1 driver which accesses the PPU registers to manage the
      domains. For slave chip's power domain, this driver is pointed such
      that this driver binds to the C2C module and the request is sent to
      slave chip over I2C and slave performs the action accordingly.
      
      Change-Id: I8146f67f9c37ca5d749fb4860f5ef58c9566383a
      Signed-off-by: Manoj Kumar's avatarManoj Kumar <manoj.kumar3@arm.com>
      6fd84614
    • Manoj Kumar's avatar
      n1sdp: fix power domain handling in C2C module · d3ce0e62
      Manoj Kumar authored
      
      
      This patch cleans the power domain API in C2C module and respective
      handling in master and slave chips.
      
      It is not possible for slave chip to report power state transition
      to master hence on slave chip, sync calls are used to power ON & OFF
      the power domains. For this purpose, C2C is treated as separate
      thread on slave chips.
      
      Change-Id: Ie356d19d5d4eeba3a62e53e9907f58c944d391b4
      Signed-off-by: Manoj Kumar's avatarManoj Kumar <manoj.kumar3@arm.com>
      d3ce0e62
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