Significant changes from 6.0.0:
* Added CPU feature bits
* Bug fixes

Declaring the form_to_visitor maps as static members caused integration problems
for some users. Instead, use a Singleton-like construction to wrap the map in
a static accessor. Additionally, use unordered_map, as we don't need the
ordered property of map.

Clang reports using bitwise-or where it expects logical-or as a warning.

In the previous change, we added a few filler values so that we were
able to add support for detecting FEAT_AFP, however the necessary
identifiers were already in place to support checking for FEAT_MTE1 and
FEAT_MTE2, so we can fill in those blanks with the necessary identifiers

Allows querying for the existence of FEAT_AFP (alternate floating-point
behavior).

While we're in the same area, we can also fill in the remaining defined
bits.

FlagM2 (bit 39, kAXFlag to VIXL) was missing from the HWCAP feature bits used
for mapping Linux's feature reporting to VIXL. This caused subsequent bits to be
off by one.

GCC 10 sometimes fails on a ternary operator used in the SVE tests. Avoid this
using a conditional.

Rerun the code coverage test and update the record.

The Markdown to HTML generator Github uses appears to want a newline after HTML
in order to recognise Markdown tags. Fix the document and generator to do this.

Fix the additional variable shadowing problems reported by Clang on MacOS.

Make it explicit that contributions to the project are covered by the cited
licence.

Fixes compilation on Debian armel, see
https://buildd.debian.org/status/fetch.php?pkg=vixl&arch=armel&ver=5.1.0-1&stamp=1637517716&raw=0

Previously, Vixl would force hard float on all arm CPUs, by checking
only for __arm__. This would cause GCC to throw an internal error when
compiling with -mfloat-abi=soft. See also this example on Compiler
Explorer: https://compiler-explorer.com/z/zsn5vaMna

Replace COMPARE_PREFIX with COMPARE in disassembler tests where the entire
output string should be tested, and fix an error revealed in the tests.

Add SVE instructions to the document, and include a linked index at the
beginning.

Prompted by https://github.com/Linaro/vixl/pull/9 enabled -Wshadow generally.

Clang 14 (current trunk) warns about the use of a bitwise operation on booleans.

Prevents -Wshadow warnings from appearing in including projects with
-Wshadow enabled.

operands-aarch64.h defines a bunch of vector register convenience
operands via the DEFINE_VREGISTERS preprocessor define, which results in
the b5 convenience operand shadowing this variable

Update the supported architecture feature table to reflect the current code and
enable the I8MM disassembler feature tests.

Change-Id: If412db4a3b0121f0626c102e4b40c21629ede8c1

Disable linter for calls to regex_match, as this causes failures for the version
of clang-tidy used in the Mac CI.

Re-generate tools/code_coverage.log as the record is too old.

Remove more switch/case constructions from the disassembler when the change to
using the decoder's provided instruction forms makes the code simpler.

Share the mapping from instruction to handler in the simulator and CPU features
auditor, removing a lot of duplicated initialisation.

Tidy up the disassembly of the scalar indexed multiply, move, addp and pmul
instructions to remove unallocated encodings.

Tidy up the disassembly of the scalar 2Reg group of instructions, and remove
unallocated encodings.

Tidy up the disassembly of the scalar shift group of instructions, and remove
unallocated encodings.

Tidy up the disassembly of the Across group of instructions, and remove
unallocated encodings.

Tidy up the disassembly of the scalar 3Same group of instructions, and remove
unallocated encodings.

Tidy up the disassembly of scalar indexed multiplies, and remove unallocated
encodings.

Tidy up the disassembly of the Mul and Shift group of instructions, and remove
unallocated encodings.

Tidy up the disassembly of the Ext and 3Diff group of instructions, and remove
unallocated encodings.

Disassemble as "unallocated" those instruction encodings in the 3Same group that
use vector formats not supported by the instruction.

Modify the NEONFormatDecoder and its uses to return substitutions involving
undefined formats as NULL, then call VisitUnallocated when encountering them.
This prevents disassembling some unallocated encodings as non-existent
instructions. Additionally, split some visitors into simpler functions that use
only one format map.

Fix the decoding of the index used for the disassembly of FMUL on D-sized
registers, and add regression tests.

Use a zero-length string when disassembling instructions which require no
arguments, and factorise those instructions into a separate handler function.

Add support for Neon vector usdot, indexed-vector usdot and sudot instructions,
available in the I8MM architecture extension.

Tidy up the simulation code for indexed element Neon operations, as already
done for the disassembly.

Use the new decoder to clean up some of the indexed element Neon disassembly
code.

Add support for SVE vector usdot, indexed-vector usdot and sudot instructions,
available in the I8MM architecture extension.