- Jan 21, 2022
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Martyn Capewell authored
Significant changes from 5.1.0: * Added SVE2 support * Added Matrix Multiply support * Changes to visitor interface - single Visit() method * Bug fixes
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mmc28a authored
Rerun the code coverage test and update the record.
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- Jan 18, 2022
- Jan 13, 2022
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Martyn Capewell authored
Make it explicit that contributions to the project are covered by the cited licence.
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Andrea Pappacoda authored
Fixes compilation on Debian armel, see https://buildd.debian.org/status/fetch.php?pkg=vixl&arch=armel&ver=5.1.0-1&stamp=1637517716&raw=0 Previously, Vixl would force hard float on all arm CPUs, by checking only for __arm__. This would cause GCC to throw an internal error when compiling with -mfloat-abi=soft. See also this example on Compiler Explorer: https://compiler-explorer.com/z/zsn5vaMna
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- Jan 11, 2022
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Martyn Capewell authored
Replace COMPARE_PREFIX with COMPARE in disassembler tests where the entire output string should be tested, and fix an error revealed in the tests.
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Martyn Capewell authored
Add SVE instructions to the document, and include a linked index at the beginning.
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- Jan 07, 2022
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Martyn Capewell authored
Prompted by https://github.com/Linaro/vixl/pull/9 enabled -Wshadow generally.
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Mike Hommey authored
Clang 14 (current trunk) warns about the use of a bitwise operation on booleans.
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Mai M authored
Prevents -Wshadow warnings from appearing in including projects with -Wshadow enabled. operands-aarch64.h defines a bunch of vector register convenience operands via the DEFINE_VREGISTERS preprocessor define, which results in the b5 convenience operand shadowing this variable
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- Jan 06, 2022
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Martyn Capewell authored
Update the supported architecture feature table to reflect the current code and enable the I8MM disassembler feature tests.
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Matthew Bentham authored
Change-Id: If412db4a3b0121f0626c102e4b40c21629ede8c1
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mmc28a authored
Disable linter for calls to regex_match, as this causes failures for the version of clang-tidy used in the Mac CI.
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- Jan 04, 2022
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TatWai Chong authored
Re-generate tools/code_coverage.log as the record is too old.
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- Dec 01, 2021
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Martyn Capewell authored
Remove more switch/case constructions from the disassembler when the change to using the decoder's provided instruction forms makes the code simpler.
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- Nov 26, 2021
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Martyn Capewell authored
Share the mapping from instruction to handler in the simulator and CPU features auditor, removing a lot of duplicated initialisation.
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Martyn Capewell authored
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- Nov 25, 2021
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Martyn Capewell authored
Tidy up the disassembly of the scalar indexed multiply, move, addp and pmul instructions to remove unallocated encodings.
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Martyn Capewell authored
Tidy up the disassembly of the scalar 2Reg group of instructions, and remove unallocated encodings.
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Martyn Capewell authored
Tidy up the disassembly of the scalar shift group of instructions, and remove unallocated encodings.
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- Nov 16, 2021
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Martyn Capewell authored
Tidy up the disassembly of the Across group of instructions, and remove unallocated encodings.
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Martyn Capewell authored
Tidy up the disassembly of the scalar 3Same group of instructions, and remove unallocated encodings.
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Martyn Capewell authored
Tidy up the disassembly of scalar indexed multiplies, and remove unallocated encodings.
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Martyn Capewell authored
Tidy up the disassembly of the Mul and Shift group of instructions, and remove unallocated encodings.
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Martyn Capewell authored
Tidy up the disassembly of the Ext and 3Diff group of instructions, and remove unallocated encodings.
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- Nov 04, 2021
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Martyn Capewell authored
Disassemble as "unallocated" those instruction encodings in the 3Same group that use vector formats not supported by the instruction.
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Martyn Capewell authored
Modify the NEONFormatDecoder and its uses to return substitutions involving undefined formats as NULL, then call VisitUnallocated when encountering them. This prevents disassembling some unallocated encodings as non-existent instructions. Additionally, split some visitors into simpler functions that use only one format map.
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- Oct 28, 2021
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Martyn Capewell authored
Fix the decoding of the index used for the disassembly of FMUL on D-sized registers, and add regression tests.
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- Oct 14, 2021
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Martyn Capewell authored
Use a zero-length string when disassembling instructions which require no arguments, and factorise those instructions into a separate handler function.
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- Oct 01, 2021
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Martyn Capewell authored
Add support for Neon vector usdot, indexed-vector usdot and sudot instructions, available in the I8MM architecture extension.
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- Sep 30, 2021
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Martyn Capewell authored
Tidy up the simulation code for indexed element Neon operations, as already done for the disassembly.
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Martyn Capewell authored
Use the new decoder to clean up some of the indexed element Neon disassembly code.
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- Sep 29, 2021
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Martyn Capewell authored
Add support for SVE vector usdot, indexed-vector usdot and sudot instructions, available in the I8MM architecture extension.
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- Sep 23, 2021
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Martyn Capewell authored
Add support for ld1ro[bhwd] instructions, and integrate with existing, similar, quad replicating loads.
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- Sep 21, 2021
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Martyn Capewell authored
The macro assembler did not directly support scalar-plus-scalar addressing mode for ld1rq and ldnt1 SVE instructions, and would fall back to a two instruction sequence instead. Fix this, and add tests for the single-instruction modes.
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- Jul 15, 2021
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Martyn Capewell authored
If code coverage data is more than a month older than the most recent commit, make test.py fail and request regeneration of test data.
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- Jul 08, 2021
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Martyn Capewell authored
Some encodings near the existing bitfield instructions should be detected as unallocated. This was causing disassembly to show negative immediate parameters and unpredictable simulation results. Fix this and add a regression test.
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- Jul 07, 2021
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Martyn Capewell authored
Fix typo in the clang-tidy script that prevented it checking the simulator, and address the new problems it's found.
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- Jun 24, 2021
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Martyn Capewell authored
Implement support for integer matrix multiplication on Neon registers.
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