Chandni Cherukuri authored Dec 05, 2018 and Sandrine Bailleux committed Dec 13, 2018

FVP_CSS_SGI-575 is the Fixed Virtual Platform on which the
Trusted-Firmware-A Tests are executed for SGI-575.

Change-Id: I606d316d251e69f5a88208b4edde132d29856b3d
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>

Chandni Cherukuri authored Nov 13, 2018 and Sandrine Bailleux committed Dec 13, 2018

SGI-575 consists of two clusters of four Cortex-A75 CPU's each.
The FVP for this platform does not support system suspend and
resume functionality as there is no wakeup source supported.
So all the system suspend and resume related tests are skipped.

Change-Id: I758069d5ad1a3e3868260960b879a5a4d6b26496
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>

Chandni Cherukuri authored Nov 13, 2018 and Sandrine Bailleux committed Dec 13, 2018

System Guidance for Infrastructure are Arm's reference server
platforms. Add mandatory functions and macros required by all
SGI platforms to execute the TF-A tests. The common files
are placed in plat/arm/sgi/common/ folder.

Change-Id: Iaf9f3fa9dfa8d95c883bcab7c1ef00ea228b6b67
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>

Hardcoding CPU to affinity level 0 and cluster to level 1 isn't correct.
This patch removes the definitions from arch.h to prevent more tests from
making this assumption. It doesn't fix the tests that are already using
them as it may be needed to do more changes to make the tests truly
generic.

Change-Id: I3e5362ef7db7769f7db98ba68ad3842f5baa3e60
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Qualify Base and Foundation FVPs as "Armv8 Architecture FVPs", to align
with the terminology used on this page:
https://developer.arm.com/products/system-design/fixed-virtual-platforms



Change-Id: Iabdcc37e0ef25373a3d4bb7d1ad964ea53e009a5
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

This service sleeps for a number of milliseconds.

Change-Id: Ib7f17142d22c8313dedc5f8037874bacbf8ed5f4
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

In order to test multiple partitions it is needed to have at least two
different partitions with different services. This way it isn't possible
to accidentally call partition A with a service of partition B and have
it work correctly.

Cactus is meant to be the main test Secure Partition. It is the one
meant to have most of the tests that a Secure Partition has to do. Ivy
is meant to be more minimalistic. In the future, Cactus may be modified
to be a S-EL1 partition while Ivy will remain as a S-EL0 partition.

Change-Id: I29d09b9f9400b58568f9b90344a4034332a6e6e1
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

This test uses a deprecated interface. Now only SPCI and SPRT are
supposed to be used.

Change-Id: I54072856eec9cef6955fd27f1639f3d99854f3c4
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Instead of using the custom SP deprecated interface, use SPRT.

Change-Id: I2e3e75aa5cc8a6b462b9bb80d83ac973eae12514
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Also, add test to check SPRT version.

Change-Id: I4e47bba998b86f460df3407d147735e873fd6cf3
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Change-Id: I2f110b4d06d2821d8bdf818ab7523a5c0a6b9ab9
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Chandni Cherukuri authored Dec 05, 2018 and Sandrine Bailleux committed Dec 11, 2018

The size of the spi_desc_table array is defined as
'PLAT_MAX_SPI_OFFSET_ID - MIN_SPI_ID' which causes
out of bound access for SPI between
'PLAT_MAX_SPI_OFFSET_ID - MIN_SPI_ID' and 'PLAT_MAX_SPI_OFFSET_ID'.

Define the correct size of spi_desc_table array as
'PLAT_MAX_SPI_OFFSET_ID + 1'.

Change-Id: I32cc6fd1d63fa4a2e04387c8ce4b56f472f834ab
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>

The tests request valid and invalid handles and close them.

Change-Id: Ie421507d8dd4793e635e82f74c206529d9ba59d0
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Change-Id: I0abd16e486aa500aed0108786dbae6eb90a49c1f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Remove code based on MM_COMMUNICATE. Remove tests based on it.

Also, remove the now empty arm_def.h.

Change-Id: I08a2680b10df3a24c67abb10e5dc07fda99f6fb9
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

This helps debugging as the elf file contains the base address of the
image so it doesn't have to be specified when loading the debug symbols.

Change-Id: Ie9dcbce3d1b3d24ff587bd9daa1839b948e98f99
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

This struct is now unused. Rather than keeping unused code in the
repository, it's better to remove it.

Change-Id: I2eb0f8c1a273df15c228ba72372b152e54f0fb27
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Create a new section for the stacks inside of BSS. SPM zeroes the
memory in any region marked as BSS, so it isn't needed to do it here.

Note that now each region (text, rodata, data, bss) need to be aligned
to a page boundary so that they can be different regions in the resource
description.

Previously the memory to be used as stack was passed in the boot info
struct. Now this is not needed as the partition can define all regions
it wants to use.

Change-Id: If330e27b0b27dde93b6c9e63b7136d23bdc7dd9e
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

This is not needed anymore. BSS, RODATA and RWDATA are defined in the
DTS file. SPM uses this information to map the corresponding memory
regions with the correct attributes so that the Secure Partition doesn't
have to do it.

Change-Id: I743b2ed2c7c9554b6af0d899a427515b1c943454
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

All information about Cactus is now described in this file.

Change-Id: Ibe4b657b6cdd1bda582b29138752ef41134db208
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

It isn't a good idea to share resources between different images. For
this reason, Cactus should use a different console than the TF and TFTF.
Future partitions should ideally use another different UART.

Change-Id: I8b61ca09b0e820bc6b9cdb400c8d55e2005a23bd
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

John Tsichritzis authored Oct 30, 2018 and Sandrine Bailleux committed Nov 29, 2018

The three parts of the "for" loops are more readable than before. The
way they are written now, it is clear which are the initial and final
values of the loop controlling variables.

Also, parentheses were added only to those macro parameters that can
receive expressions as arguments. E.g. in for_each_cpu(cpu), "cpu" must
receive a variable name, it cannot receive an expression. So there was
no reason to clutter the macro body with unnecessary parentheses
wherever "cpu" parameter appears. Parentheses were added only around
those parameters that might receive expressions.

The parameters in for_each_cpu_in_power_domain were swapped. This was
done for consistency with the other two macros. Thus, the first
parameter is always the iterating variable, in all macros.

Change-Id: I18831237840e9cfa738a48dbe7f1ec449c89f7af
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>

BL1 SMC function IDs are not platform-specific so move them to a new
generic header file, called bl1.h.

Change-Id: I621483f7737f8101e9f370343e1a45a731c31c3b
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

The SMC function identifier is always a 32-bit integer, regardless of
the caller's execution state and of the SMC calling convention in use.

Change-Id: I8d4f7b9efcea3f00ac2ff0a397ca0d8ab824eecb
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

Antonio Nino Diaz authored Nov 23, 2018 and Sandrine Bailleux committed Nov 26, 2018

Some of the affected macros can only be used from C code. In general, we
use arch_helpers.h for any C helpers to access registers. For
consistency, the other macros have been moved as well.

Change-Id: If27ee82b067d920d7b338c0a1b6e61a6ec078f4f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Antonio Nino Diaz authored Nov 23, 2018 and Sandrine Bailleux committed Nov 26, 2018

Change-Id: If643498433dfa2007703227226064b9d12f4c242
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Antonio Nino Diaz authored Nov 22, 2018 and Sandrine Bailleux committed Nov 26, 2018

Change-Id: I55a567014023d593ec96dd9eff71bfca01db9c61
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Change-Id: I16127da5f14b53e06201be8c03d70afde8f7ad8e
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

The headers forked at some point in the past and have diverged a lot. In
order to make it easier to share code between TF-A-Tests and TF-A, this
patch synchronises most of the definitions in the mentioned headers.

This is not a complete sync, it has to be followed by more cleanup.

Change-Id: I35c1b928cb4c06ae52483406c933e5f11cb47bf8
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Change-Id: Ibf4fffbfc025b205223d17a579f8cde386252199
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Code that originates from the Trusted Firmware-A project expects the
stdlib headers to work in a specific way and to have some specific
defines. Specifically, TF-A doesn't have the non-standard types.h
header, and it has all the definitions in stdint.h.

Also, the __init define is missing. No component of this repository
needs this option, but having the define in cdefs.h allows code sharing
between both projects.

Change-Id: Ic298fd87a6c2cf8a9e5b8a18fc274d4150ed0a13
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

The purpose of these macros is unclear - is it tracking the exact
SMCCC version expected by the TF-A Tests, or the maximum version, or
something else? Besides, they are not used in the source tree so
better to remove them as to avoid any confusion.

Change-Id: Ieb426dc9c54f19b0907d3221bb5606e03c9e360f
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

We don't use semihosting in any of our test configs at the moment so
there's a risk this code might get broken without us notifying it.
It seems better to reintroduce it if and when we actually need it.

Change-Id: Iae84e3be034cc3da0248954aa5a1029ddd50aabb
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

We always use the text report on the UART so drop the other report
formats (Junit) and destinations (file over semihosting). This
simplifies the report generation code.

Change-Id: I64e105d8c773e31d63a4ed06999d24f946a40014
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

TF-A and TF-A Tests git repositories are getting moved to a TF-A/
namespace in order to easily identify what repos are for TF-A or TF-M.

Change-Id: Id3e9ae299fa4e0dd8699c967879cd8ce5a17c940
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

John Tsichritzis authored Oct 25, 2018 and Sandrine Bailleux committed Nov 06, 2018

Change-Id: Id05eebb811d4c23c6a2bfdfb4762bb659b97a4bf
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>

Jeenu Viswambharan authored Oct 16, 2018 and Sandrine Bailleux committed Oct 31, 2018

EL3 runtime firmware currently enables unconditional access to pointer
authentication registers from lower EL [1]. The test performs a read
access on a pointer authentication system register to ensure that the
access is permitted from a lower EL, and doesn't result in a trap to
EL3.

[1] https://github.com/ARM-software/arm-trusted-firmware/commit/3ff4aaaca44b75504aec5ab5b72cd587a6fcd432



Change-Id: I893604ebcd9e5df830d97cce405c2a7518c0b23c
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

Change-Id: I54b213bbdb13e21d8d0919b76eebf6c85e1fa691
Signed-off-by: Sathees Balya <sathees.balya@arm.com>

Print the cluster and cpu ID in the output.  It is useful to know
which cpu is part of which cluster as that helps with the data
visualization.

Change-Id: Id02745d677abc4d4e9c2e289917da6d67e7b93b2
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>

At the moment, alignment fault checking is always enabled in TF-A
Tests (by setting the HSCTLR/SCTLR.A bit). Thus, for every instruction
that loads or stores one or more registers, the hardware checks that
the address being accessed is properly aligned to the size of the data
element(s) being accessed. If this check fails it causes an alignment
fault, which is taken as a data abort exception.

However, the compiler is currently unaware that it must not emit load
and store instructions resulting in unaligned accesses because we do
not compile the source code with -mstrict-align (AArch64) /
-mno-unaligned-access (AArch32). Because of this, we might get some
unexpected alignment faults.

We could request the compiler to align all data accesses but whether
this gives us any performance benefit is dependent on the
microarchitecture. Thus, it is simpler to just disable hardware
alignment checking and let the compiler make the call.

Change-Id: I6ef4afb09e0f87c8462a968da1ca2192ee075b40
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>