Disable hardware alignment checking

At the moment, alignment fault checking is always enabled in TF-A
Tests (by setting the HSCTLR/SCTLR.A bit). Thus, for every instruction
that loads or stores one or more registers, the hardware checks that
the address being accessed is properly aligned to the size of the data
element(s) being accessed. If this check fails it causes an alignment
fault, which is taken as a data abort exception.

However, the compiler is currently unaware that it must not emit load
and store instructions resulting in unaligned accesses because we do
not compile the source code with -mstrict-align (AArch64) /
-mno-unaligned-access (AArch32). Because of this, we might get some
unexpected alignment faults.

We could request the compiler to align all data accesses but whether
this gives us any performance benefit is dependent on the
microarchitecture. Thus, it is simpler to just disable hardware
alignment checking and let the compiler make the call.

Change-Id: I6ef4afb09e0f87c8462a968da1ca2192ee075b40
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>