- Aug 03, 2022
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John Garry authored
All the many other configs depend on config PINCTRL_MSM, yet for config PINCTRL_SM8450 we select config PINCTRL_MSM. Make config PINCTRL_SM8450 depend on PINCTRL_MSM to be consistent with the rest. Signed-off-by:
John Garry <john.garry@huawei.com> Suggested-by:
Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/1658829764-124936-1-git-send-email-john.garry@huawei.com Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Jianhua Lu authored
Fix the PDC mapping for SM8250, gpio39 is mapped to irq73(not irq37). Fixes: b41efeed("pinctrl: qcom: sm8250: Specify PDC map.") Signed-off-by:
Jianhua Lu <lujianhua000@gmail.com> Reviewed-by:
Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20220803015645.22388-1-lujianhua000@gmail.com Signed-off-by:
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Mario Limonciello authored
`char *output_enable` is no longer used once switching to unicode output. Fixes: e8129a07 ("pinctrl: amd: Use unicode for debugfs output") Reported-by:
kernel test robot <lkp@intel.com> Signed-off-by:
Mario Limonciello <mario.limonciello@amd.com> Link: https://lore.kernel.org/r/20220801144952.141-1-mario.limonciello@amd.com Signed-off-by:
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- Jul 26, 2022
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Mario Limonciello authored
The output is currently split across two lines making it more difficult to parse unless the newlines are removed between pins or it's read in by a parser like Libreoffice Calc or Google docs. To make it easier to follow to the naked eye in a terminal window: * drop the newline in the middle of pin definitions * shorten all output using unicode characters * align all pipe delimitters * output the same phrase even for disabled functions (but with a ∅ character) Signed-off-by:
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Mario Limonciello authored
Currently the debugfs output for pinctrl-amd puts the first line combined with "GPIO bank". This makes it a little harder to process as the file needs to be manually corrected for the mistake. Change this to be a new line character instead. Signed-off-by:
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Slark Xiao authored
Replace 'the the' with 'the' in the comment. Signed-off-by:
Slark Xiao <slark_xiao@163.com> Link: https://lore.kernel.org/r/20220722092419.77052-1-slark_xiao@163.com Signed-off-by:
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Xin Gao authored
Missing a blank line after declarations. Signed-off-by:
Xin Gao <gaoxin@cdjrlc.com> Link: https://lore.kernel.org/r/20220719182647.9038-1-gaoxin@cdjrlc.com Signed-off-by:
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Konrad Dybcio authored
Add a driver to control the TLMM block on SM6375. This is an adapted version of msm-5.4's pinctrl-blair driver. Signed-off-by:
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- Jul 18, 2022
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Vladimir Oltean authored
The irqchip->irq_set_type method is called by __irq_set_trigger() under the desc->lock raw spinlock. The armada-37xx implementation, armada_37xx_irq_set_type(), uses an MMIO regmap created by of_syscon_register(), which uses plain spinlocks (the kind that are sleepable on RT). Therefore, this is an invalid locking scheme for which we get a kernel splat stating just that ("[ BUG: Invalid wait context ]"), because the context in which the plain spinlock may sleep is atomic due to the raw spinlock. We need to go raw spinlocks all the way. Make this driver create its own MMIO regmap, with use_raw_spinlock=true, and stop relying on syscon to provide it. This patch depends on commit 67021f25 ("regmap: teach regmap to use raw spinlocks if requested in the config"). Cc: <stable@vger.kernel.org> # 5.15+ Fixes: 2f227605 ("pinctrl: armada-37xx: Add irqchip support") Signed-off-by:Vladimir Oltean <vladimir.oltean@nxp.com> Link: https://lore.kernel.org/r/20220716233745.1704677-3-vladimir.oltean@nxp.com Signed-off-by:
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Vladimir Oltean authored
The irqchip->irq_set_type method is called by __irq_set_trigger() under the desc->lock raw spinlock. The armada-37xx implementation, armada_37xx_irq_set_type(), takes a plain spinlock, the kind that becomes sleepable on RT. Therefore, this is an invalid locking scheme for which we get a kernel splat stating just that ("[ BUG: Invalid wait context ]"), because the context in which the plain spinlock may sleep is atomic due to the raw spinlock. We need to go raw spinlocks all the way. Replace the driver's irq_lock with a raw spinlock, to disable preemption even on RT. Cc: <stable@vger.kernel.org> # 5.15+ Fixes: 2f227605 ("pinctrl: armada-37xx: Add irqchip support") Signed-off-by: -
Mario Limonciello authored
It was observed that by allowing pinctrl_amd to be loaded later in the boot process that interrupts sent to the GPIO controller early in the boot are not serviced. The kernel treats these as a spurious IRQ and disables the IRQ. This problem was exacerbated because it happened on a system with an encrypted partition so the kernel object was not accesssible for an extended period of time while waiting for a passphrase. To avoid this situation from occurring, stop allowing pinctrl-amd from being built as a module and instead require it to be built-in or disabled. Reported-by:
<madcatx@atlas.cz> Suggested-by:
<jwrdegoede@fedoraproject.org> Link: https://bugzilla.kernel.org/show_bug.cgi?id=216230 Signed-off-by:
Hans de Goede <hdegoede@redhat.com> Link: https://lore.kernel.org/r/20220713175950.964-1-mario.limonciello@amd.com Signed-off-by:
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Linus Walleij authored
This reverts commit 7542766e. It was noted during follow-up that the approach is incorrect. Signed-off-by:
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Fabio Estevam authored
Pass MODULE_DEVICE_TABLE() so that module autoloading can work. This also aligns with the other i.MX8 pinctrl drivers. Signed-off-by:
Fabio Estevam <festevam@denx.de> Reviewed-by:
Jacky Bai <ping.bai@nxp.com> Link: https://lore.kernel.org/r/20220712115154.2348971-1-festevam@denx.de Signed-off-by:
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Samuel Holland authored
This SoC contains a pinctrl with a new register layout. Use the variant parameter to set the right register offsets. This pinctrl also increases the number of functions per pin from 8 to 16, taking advantage of all 4 bits in the mux config field (so far, only functions 0-8 and 14-15 are used). This increases the maximum possible number of functions. Reviewed-by:
Heiko Stuebner <heiko@sntech.de> Tested-by:
Samuel Holland <samuel@sholland.org> Reviewed-by:
Andre Przywara <andre.przywara@arm.com> Link: https://lore.kernel.org/r/20220713025233.27248-7-samuel@sholland.org Signed-off-by:
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Samuel Holland authored
Starting with the D1/D1s/T113 SoC, Allwinner changed the layout of the pinctrl registers. This new layout widens the drive level field, which affects the pull register offset and the overall bank size. In order to support multiple register layouts, some of the layout parameters need to be set based on the pinctrl variant. This requires passing the pinctrl struct pointer to the register/offset calculation functions. Reviewed-by:
Jernej Skrabec <jernej.skrabec@gmail.com> Reviewed-by:
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Samuel Holland authored
Starting with the D1/D1s/T113 SoC, Allwinner changed the layout of the pinctrl registers. This new layout widens the drive level field, which affects the pull register offset and the overall bank size. As a first step to support this, combine the register and offset calculation functions, and refactor the math to depend on one constant for field widths instead of three. This minimizes the code size impact of making some of the factors dynamic. While rewriting these functions, move them to the implementation file, since that is the only file where they are used. And make the comment more generic, without mentioning specific offsets/sizes. The callers are updated to expect a shifted mask, and to use consistent terminology (reg/shift/mask/val). Reviewed-by:
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Samuel Holland authored
H616 and newer SoCs feature a 2.5V I/O bias mode in addition to the 1.8V and 3.3V modes. This mode is entered by selecting the 3.3V level and disabling the "withstand function". H616 supports this capability on its main PIO only. A100 supports this capability on both its PIO and R-PIO. Reviewed-by:
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Samuel Holland authored
H6 requires I/O bias configuration on both of its PIO devices. Previously it was only done for the main PIO. The setting for Port L is at bit 0, so the bank calculation needs to account for the pin base. Otherwise the wrong bit is used. Fixes: cc62383f ("pinctrl: sunxi: Support I/O bias voltage setting on H6") Reviewed-by:
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Robert Marko authored
PMP8074 has 12 GPIO-s with holes on GPIO1 and GPIO12. Signed-off-by:
Robert Marko <robimarko@gmail.com> Link: https://lore.kernel.org/r/20220711203408.2949888-4-robimarko@gmail.com Signed-off-by:
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Dominik Kobinski authored
Add support for pm8226 SPMI GPIOs. The PMIC features 8 GPIOs, with no holes inbetween. Reviewed-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Suggested-by:
Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> Signed-off-by:
Dominik Kobinski <dominikkobinski314@gmail.com> Link: https://lore.kernel.org/r/20211125215310.62371-1-dominikkobinski314@gmail.com Signed-off-by:
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Andy Shevchenko authored
Instead of open coding, use device_match_of_node() helper. Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20220629115840.16241-1-andriy.shevchenko@linux.intel.com Signed-off-by:
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Claudiu Beznea authored
Remove #ifdef CONFIG_PM and use pm_ptr() macro instead. Signed-off-by:
Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220704101253.808519-2-claudiu.beznea@microchip.com Signed-off-by:
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Claudiu Beznea authored
Remove #ifdef CONFIG_PM_SLEEP and use pm_sleep_ptr() macro instead. Signed-off-by:
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Horatiu Vultur authored
The blamed commit changed to use regmaps instead of __iomem. But it didn't update the register offsets to be at word offset, so it uses byte offset. Another issue with the same commit is that it has a limit of 32 registers which is incorrect. The sparx5 has 64 while lan966x has 77. Fixes: 076d9e71 ("pinctrl: ocelot: convert pinctrl to regmap") Acked-by:
Colin Foster <colin.foster@in-advantage.com> Reviewed-by:
Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by:
Horatiu Vultur <horatiu.vultur@microchip.com> Link: https://lore.kernel.org/r/20220713193750.4079621-3-horatiu.vultur@microchip.com Signed-off-by:
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Horatiu Vultur authored
The blamed commit introduce support for lan966x which use the same pinconf_ops as sparx5. The problem is that pinconf_ops is specific to sparx5. More precisely the offset of the bits in the pincfg register are different and also lan966x doesn't have support for PIN_CONFIG_INPUT_SCHMITT_ENABLE. Fix this by making pinconf_ops more generic such that it can be also used by lan966x. This is done by introducing 'ocelot_pincfg_data' which contains the offset and what is supported for each SOC. Fixes: 531d6ab3 ("pinctrl: ocelot: Extend support for lan966x") Signed-off-by:
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- Jul 16, 2022
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Michael Walle authored
Since recently, the kernel is nagging about mutable irq_chips: [ 2.593426] gpio gpiochip0: (ocelot-gpio): not an immutable chip, please consider fixing it! Make it const, flag it as IRQCHIP_IMMUTABLE, add the new helper functions and call the appropriate gpiolib functions. Signed-off-by:
Michael Walle <michael@walle.cc> Acked-by:
Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220706151553.1580790-2-michael@walle.cc
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- Jul 14, 2022
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Andy Shevchenko authored
In some cases we may get a platform device that has ACPI companion which is different to the pin control described in the ACPI tables. This is primarily happens when device is instantiated by board file. In order to allow this device being enumerated, refactor intel_pinctrl_get_soc_data() to check the matching data instead of ACPI companion. Reported-by:
Henning Schild <henning.schild@siemens.com> Signed-off-by:
Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by:
Lee Jones <lee@kernel.org>
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- Jul 11, 2022
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William Dean authored
As the potential failure of the kcalloc(), it should be better to check it in order to avoid the dereference of the NULL pointer. Fixes: aa74c44b ("pinctrl: Add driver for Sunplus SP7021") Reported-by:
Hacash Robot <hacashRobot@santino.com> Signed-off-by:
William Dean <williamsukatube@gmail.com> Link: https://lore.kernel.org/r/20220710154822.2610801-1-williamsukatube@163.com Signed-off-by:
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William Dean authored
Because of the possible failure of the allocation, data->domains might be NULL pointer and will cause the dereference of the NULL pointer later. Therefore, it might be better to check it and directly return -ENOMEM without releasing data manually if fails, because the comment of the devm_kmalloc() says "Memory allocated with this function is automatically freed on driver detach.". Fixes: a86854d0 ("treewide: devm_kzalloc() -> devm_kcalloc()") Reported-by:
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Stephan Gerhold authored
Make it possible to control pins using the TLMM block in the MSM8909 SoC by adding the necessary definitions for GPIOs, groups and functions. The driver is originally taken from the msm-4.9 release [1] from Qualcomm, but cleaned up significantly with several fixes and clarifications. [1]: https://git.codelinaro.org/clo/la/kernel/msm-4.9/-/blob/LF.UM.8.7-22500-8x09.0/drivers/pinctrl/qcom/pinctrl-msm8909.c Signed-off-by:
Stephan Gerhold <stephan.gerhold@kernkonzept.com> Reviewed-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220628145502.4158234-3-stephan.gerhold@kernkonzept.com Signed-off-by:
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Jianlong Huang authored
The pinctrl dt_node_to_map method may be called in parallel which leads us to call pinconf_generic_add_group and pinconf_generic_add_function in parallel. This is not supported though and leads to errors, so add a mutex to serialize these calls. Signed-off-by:
Jianlong Huang <jianlong.huang@starfivetech.com> Signed-off-by:
Emil Renner Berthing <kernel@esmil.dk> Link: https://lore.kernel.org/r/20220627085333.1774396-1-emil.renner.berthing@canonical.com Signed-off-by:
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- Jul 10, 2022
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Lad Prabhakar authored
Add IRQ domain to RZ/G2L pinctrl driver to handle GPIO interrupt. GPIO0-GPIO122 pins can be used as IRQ lines but only 32 pins can be used as IRQ lines at a given time. Selection of pins as IRQ lines is handled by IA55 (which is the IRQC block) which sits in between the GPIO and GIC. Signed-off-by:
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by:
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Marc Zyngier authored
The gpiolib is unique in the way it uses intermediate fwspecs when feeding an interrupt specifier to the parent domain, as it relies on the populate_parent_alloc_arg() callback to perform a dynamic allocation. This is pretty inefficient (we free the structure almost immediately), and the only reason this isn't a stack allocation is that our ThunderX friend uses MSIs rather than a FW-constructed structure. Let's solve it by providing a new type composed of the union of a struct irq_fwspec and a msi_info_t, which satisfies both requirements. This allows us to use a stack allocation, and we can move the handful of users to this new scheme. Also perform some additional cleanup, such as getting rid of the stub versions of the irq_domain_translate_*cell helpers, which are never used when CONFIG_IRQ_DOMAIN_HIERARCHY isn't selected. Tested on a Tegra186. Reviewed-by:
Bartosz Golaszewski <brgl@bgdev.pl> Link: https://lore.kernel.org/r/20220707182314.66610-2-prabhakar.mahadev-lad.rj@bp.renesas.com
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- Jul 09, 2022
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Basavaraj Natikar authored
Remove contact information. Signed-off-by:
Basavaraj Natikar <Basavaraj.Natikar@amd.com> Link: https://lore.kernel.org/r/20220613064127.220416-4-Basavaraj.Natikar@amd.com Signed-off-by:
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Basavaraj Natikar authored
Saving/restoring interrupt and wake status bits across suspend can cause the suspend to fail if an IRQ is serviced across the suspend cycle. Signed-off-by:
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Basavaraj Natikar authored
Use devm_platform_get_and_ioremap_resource() to simplify code. Signed-off-by:
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Robert Marko authored
Commit 6c846d02 ("gpio: Don't fiddle with irqchips marked as immutable") added a warning to indicate if the gpiolib is altering the internals of irqchips. Following this change the following warning is now observed for the SPMI PMIC pinctrl driver: gpio gpiochip1: (200f000.spmi:pmic@0:gpio@c000): not an immutable chip, please consider fixing it! Fix this by making the irqchip in the SPMI PMIC pinctrl driver immutable. Signed-off-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Tested-by:
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- Jul 05, 2022
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Kuninori Morimoto authored
AVB1 needs MODSEL6, AVB2 needs MODSEL5 settings. This patch adds missing MODSELx settings for the affected pins. Signed-off-by:
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/r/87k08xsj81.wl-kuninori.morimoto.gx@renesas.com Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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Kuninori Morimoto authored
TSN0 needs MODSEL4 settings. This patch adds missing MODSELx settings for the affected pins. Signed-off-by:
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Kuninori Morimoto authored
This patch adds missing ERROROUTC_A settings. Current existing ERROROUTC should be _B, this patch tidies it up. Signed-off-by:
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