Vincent Donnefort authored Aug 29, 2022 and Deepak Kumar Mishra committed Dec 20, 2022

The new sysctl sched_pelt_multiplier allows a user to set a clock
multiplier to x2 or x4 (x1 being the default). This clock multiplier
artificially speeds up PELT ramp up/down similarly to use a faster
half-life than the default 32ms.

  - x1: 32ms half-life
  - x2: 16ms half-life
  - x4: 8ms  half-life

Internally, a new clock is created: rq->clock_task_mult. It sits in the
clock hierarchy between rq->clock_task and rq->clock_pelt.

[peterz: Use sched_feat()]
Signed-off-by: Vincent Donnefort <vincent.donnefort@arm.com>
Signed-off-by: Dietmar Eggemann <dietmar.eggemann@arm.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>

Pierre Gondois authored Oct 25, 2022 and Deepak Kumar Mishra committed Dec 20, 2022

commit 3fcbf1c7 ("arch_topology: Fix cache attributes detection
in the CPU hotplug path")
adds a call to detect_cache_attributes() to populate the cacheinfo
before updating the siblings mask. detect_cache_attributes() allocates
memory and can take the PPTT mutex (on ACPI platforms). On PREEMPT_RT
kernels, on secondary CPUs, this triggers a:
  'BUG: sleeping function called from invalid context' [1]
as the code is executed with preemption and interrupts disabled.

The primary CPU was previously storing the cache information using
the now removed (struct cpu_topology).llc_id:
commit 5b8dc787 ("arch_topology: Drop LLC identifier stash from
the CPU topology")

allocate_cache_info() tries to build the cacheinfo from the primary
CPU prior secondary CPUs boot, if the DT/ACPI description
contains cache information.
If allocate_cache_info() fails, then fallback to the current state
for the cacheinfo allocation. [1] will be triggered in such case.

When unplugging a CPU, the cacheinfo memory cannot be freed. If it
was, then the memory would be allocated early by the re-plugged
CPU and would trigger [1].

[1]:
[    7.560791] BUG: sleeping function called from invalid context at kernel/locking/spinlock_rt.c:46
[    7.560794] in_atomic(): 1, irqs_disabled(): 128, non_block: 0, pid: 0, name: swapper/111
[    7.560796] preempt_count: 1, expected: 0
[    7.560797] RCU nest depth: 1, expected: 1
[    7.560799] 3 locks held by swapper/111/0:
[    7.560800]  #0: ffff403e406cae98 (&pcp->lock){+.+.}-{3:3}, at: get_page_from_freelist+0x218/0x12c8
[    7.560811]  #1: ffffc5f8ed09f8e8 (rcu_read_lock){....}-{1:3}, at: rt_spin_trylock+0x48/0xf0
[    7.560820]  #2: ffff403f400b4fd8 (&zone->lock){+.+.}-{3:3}, at: rmqueue_bulk+0x64/0xa80
[    7.560824] irq event stamp: 0
[    7.560825] hardirqs last  enabled at (0): [<0000000000000000>] 0x0
[    7.560827] hardirqs last disabled at (0): [<ffffc5f8e9f7d594>] copy_process+0x5dc/0x1ab8
[    7.560830] softirqs last  enabled at (0): [<ffffc5f8e9f7d594>] copy_process+0x5dc/0x1ab8
[    7.560833] softirqs last disabled at (0): [<0000000000000000>] 0x0
[    7.560834] Preemption disabled at:
[    7.560835] [<ffffc5f8e9fd3c28>] migrate_enable+0x30/0x130
[    7.560838] CPU: 111 PID: 0 Comm: swapper/111 Tainted: G        W          6.0.0-rc4-rt6-[...]
[    7.560841] Call trace:
[...]
[    7.560870]  __kmalloc+0xbc/0x1e8
[    7.560873]  detect_cache_attributes+0x2d4/0x5f0
[    7.560876]  update_siblings_masks+0x30/0x368
[    7.560880]  store_cpu_topology+0x78/0xb8
[    7.560883]  secondary_start_kernel+0xd0/0x198
[    7.560885]  __secondary_switched+0xb0/0xb4

Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>

Pierre Gondois authored Oct 24, 2022 and Deepak Kumar Mishra committed Dec 20, 2022

acpi_find_last_cache_level() allows to find the last level of cache
for a given CPU. The function is only called on arm64 ACPI based
platforms to check for cache information that would be missing in
the CLIDR_EL1 register.
To allow populating (struct cpu_cacheinfo).num_leaves by only parsing
a PPTT, update acpi_find_last_cache_level() to get the 'split_levels',
i.e. the number of cache levels being split in data/instruction
caches.

It is assumed that there will not be data/instruction caches above a
unified cache.
If a split level consist of one data cache and no instruction cache
(or opposite), then the missing cache will still be populated
by default with minimal cache information, and maximal cpumask
(all non-existing caches have the same fw_token).

Suggested-by: Jeremy Linton <jeremy.linton@arm.com>
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Jeremy Linton <jeremy.linton@arm.com>

Pierre Gondois authored Oct 13, 2022 and Deepak Kumar Mishra committed Dec 20, 2022

acpi_find_cache_levels() is used at a single place and is short
enough to be merged into the calling function. The removal allows
an easier renaming of the calling function in the next patch.

Also reorder the local variables in the 'reversed Christmas tree'
order.

Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Sudeep Holla <sudeep.holla@arm.com>
Reviewed-by: Jeremy Linton <jeremy.linton@arm.com>

Pierre Gondois authored Oct 24, 2022 and Deepak Kumar Mishra committed Dec 20, 2022

Make init_of_cache_level() return an error code when the cache
information parsing fails to help detecting missing information.

init_of_cache_level() is only called for riscv. Returning an error
code instead of 0 will prevent detect_cache_attributes() to allocate
memory if an incomplete DT is parsed.

Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Sudeep Holla <sudeep.holla@arm.com>

Pierre Gondois authored Oct 24, 2022 and Deepak Kumar Mishra committed Dec 20, 2022

RISC-V's implementation of init_of_cache_level() is following
the Devicetree Specification v0.3 regarding caches, cf.:
- s3.7.3 'Internal (L1) Cache Properties'
- s3.8 'Multi-level and Shared Cache Nodes'

Allow reusing the implementation by moving it.

Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Sudeep Holla <sudeep.holla@arm.com>

Pierre Gondois authored Nov 15, 2022 and Deepak Kumar Mishra committed Dec 20, 2022

fw_token is used for DT/ACPI systems to identify CPUs sharing caches.
For DT based systems, fw_token is set to a pointer to a DT node.

commit 3da72e18 ("cacheinfo: Decrement refcount in
cache_setup_of_node()")
doesn't increment the refcount of fw_token anymore in
cache_setup_of_node(). fw_token is indeed used as a token and not
as a (struct device_node*), so no reference to fw_token should be
kept.

However, [1] is triggered when hotplugging a CPU multiple times
since cache_shared_cpu_map_remove() decrements the refcount to
fw_token at each CPU unplugging, eventually reaching 0.

Remove of_node_put() for fw_token in cache_shared_cpu_map_remove().

[1]
------------[ cut here ]------------
refcount_t: saturated; leaking memory.
WARNING: CPU: 4 PID: 32 at lib/refcount.c:22 refcount_warn_saturate (lib/refcount.c:22 (discriminator 3))
Modules linked in:
CPU: 4 PID: 32 Comm: cpuhp/4 Tainted: G        W          6.1.0-rc1-14091-g9fdf2ca7b9c8 #76
Hardware name: ARM LTD ARM Juno Development Platform/ARM Juno Development Platform, BIOS EDK II Oct 31 2022
pstate: 600000c5 (nZCv daIF -PAN -UAO -TCO -DIT -SSBS BTYPE=--)
pc : refcount_warn_saturate (lib/refcount.c:22 (discriminator 3))
lr : refcount_warn_saturate (lib/refcount.c:22 (discriminator 3))
[...]
Call trace:
[...]
of_node_release (drivers/of/dynamic.c:335)
kobject_put (lib/kobject.c:677 lib/kobject.c:704 ./include/linux/kref.h:65 lib/kobject.c:721)
of_node_put (drivers/of/dynamic.c:49)
free_cache_attributes.part.0 (drivers/base/cacheinfo.c:712)
cacheinfo_cpu_pre_down (drivers/base/cacheinfo.c:718)
cpuhp_invoke_callback (kernel/cpu.c:247 (discriminator 4))
cpuhp_thread_fun (kernel/cpu.c:785)
smpboot_thread_fn (kernel/smpboot.c:164 (discriminator 3))
kthread (kernel/kthread.c:376)
ret_from_fork (arch/arm64/kernel/entry.S:861)
---[ end trace 0000000000000000 ]---

Fixes: 3da72e18 ("cacheinfo: Decrement refcount in cache_setup_of_node()")
Reported-by: Geert Uytterhoeven <geert@linux-m68k.org>
Reported-by: Marek Szyprowski <m.szyprowski@samsung.com>
Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Sudeep Holla <sudeep.holla@arm.com>
Reviewed-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>

Pierre Gondois authored Oct 13, 2022 and Deepak Kumar Mishra committed Dec 20, 2022

Refcounts to DT nodes are only incremented in the function
and never decremented. Decrease the refcounts when necessary.

Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>

Valentin Schneider authored Sep 30, 2020 and Deepak Kumar Mishra committed Dec 20, 2022

The cpufreq cooling devices have been removed by

  52e3b2ca ("arm64: dts: qcom: sdm845: Remove cpufreq cooling devices for CPU thermal zones")

but the per-CPU thermal zones remain. Per monitor_thermal_zone(), we get
one polling workqueue per TZ, which is a lot of noise considering the only
time those thermal zones will affect the system will be upon crossing a
critical trip point.

Remove the per-CPU thermal zones and let the cluster-wide ones handle
critical temperature trip points.

Signed-off-by: Valentin Schneider <valentin.schneider@arm.com>

Morten Rasmussen authored Jan 18, 2021 and Deepak Kumar Mishra committed Dec 20, 2022

This is a temporary hack.

Currently trace points for PELT are only triggered when the PELT metrics
consumed by the scheduler are actually updated, i.e. util_avg. This
means no updates if no 1 ms boundary is being crossed by the update.
When reconstructing the PELT signal based on this data, the peak PELT
value can therefore be up to 1 ms worth of PELT accumulation off (23 in
absolute terms). This leads to a discrepancy that causes test cases to
fail.

This patch ensures that trace events are always emitted even if the
metrics haven't been updated which should allow accurate reconstruction
of the PELT signals.

Ionela Voinescu authored Nov 23, 2021 and Deepak Kumar Mishra committed Dec 20, 2022

Signed-off-by: Ionela Voinescu <ionela.voinescu@arm.com>

Dietmar Eggemann authored Sep 02, 2020 and Deepak Kumar Mishra committed Dec 20, 2022

arm and arm64:

    Add    Debug per_cpu maps access
    Add    Prove Locking
    Add    Scheduler statistics

arm:

    Add    kernel .config support and /proc/config.gz

arm64:

    Add    Scheduler debugging
    Add    Ftrace

Signed-off-by: Dietmar Eggemann <dietmar.eggemann@arm.com>

Dietmar Eggemann authored Sep 02, 2020 and Deepak Kumar Mishra committed Dec 20, 2022

arm and arm64:

    Add    Cgroups (+ FAIR_GROUP_SCHED and FREEZER)
    Add    Uclamp support for tasks and taskgroups
    Add    CpuFreq governors and make schedutil default

arm:

    Add    Cpuset support
    Add    Scheduler autogroups
    Add    DIE (SCHED_MC) sched domain level
    Add    Energy Model

Signed-off-by: Dietmar Eggemann <dietmar.eggemann@arm.com>
Signed-off-by: Ionela Voinescu <ionela.voinescu@arm.com>
[@Ionela: cpufreq governor enablement for both arm and arm64]

Ionela Voinescu authored Sep 02, 2020 and Deepak Kumar Mishra committed Dec 20, 2022

This reverts commit 5d777b18.

[ionela.voinescu@arm.com: modify capacity of current CPU only]

Ionela Voinescu authored Sep 01, 2020 and Deepak Kumar Mishra committed Dec 20, 2022

These configs are causing instability on Juno boards.

Ionela Voinescu authored Sep 20, 2022 and Deepak Kumar Mishra committed Dec 20, 2022

For Arm:
  Add       ARM vexpress-spc cpufreq driver
  Add       ARM Big.Little cpuidle driver
  Add       Sensor Vexpress
  Disable   CONFIG_HARDEN_BRANCH_HISTORY

* acpi-x86:
  ACPI: x86: Add skip i2c clients quirk for Medion Lifetab S10346

* pm-core:
  PM: runtime: Adjust white space in the core code

* acpi-thermal:
  ACPI: thermal: Adjust critical.flags.valid check

* acpi-processor:
  ACPI: processor: perflib: Adjust acpi_processor_notify_smm() return value
  ACPI: processor: perflib: Rearrange acpi_processor_notify_smm()
  ACPI: processor: perflib: Rearrange unregistration routine
  ACPI: processor: perflib: Drop redundant parentheses
  ACPI: processor: perflib: Adjust white space
  ACPI: processor: idle: Drop unnecessary statements and parens

* acpi-apei:
  ACPI: APEI: EINJ: Refactor available_error_type_show()
  ACPI: APEI: EINJ: Fix formatting errors

The Medion Lifetab S10346 is a x86 tablet which ships with Android x86 as
factory OS. The Android x86 kernel fork ignores I2C devices described in
the DSDT, except for the PMIC and Audio codecs.

As usual the Medion Lifetab S10346's DSDT contains a bunch of extra I2C
devices which are not actually there, causing various resource conflicts.
Add an ACPI_QUIRK_SKIP_I2C_CLIENTS quirk for the Medion Lifetab S10346 to
the acpi_quirk_skip_dmi_ids table to woraround this.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>

Some inconsistent usage of white space in the PM-runtime core code
causes that code to be somewhat harder to read that it would have
been otherwise, so adjust the white space in there to be more
consistent with the rest of the code.

No expected functional impact.

Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>

Move error type descriptions into an array and loop over error types
to improve readability and maintainability.

Replace seq_printf() with seq_puts() as recommended by checkpatch.pl.

Signed-off-by: Jay Lu <jaylu102@amd.com>
Co-developed-by: Ben Cheatham <benjamin.cheatham@amd.com>
Signed-off-by: Ben Cheatham <benjamin.cheatham@amd.com>
Reviewed-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>

Checkpatch reveals warnings and an error due to missing lines and
incorrect indentations. Add the missing lines after declarations and
fix the suspect indentations.

Signed-off-by: Jay Lu <jaylu102@amd.com>
Signed-off-by: Ben Cheatham <benjamin.cheatham@amd.com>
Reviewed-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>

Avoid returning a confusing error code from acpi_processor_notify_smm()
if it is called for the second time in the case when SMM notification
regarding P-state control is not supported.

Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>

Rearrange the code in acpi_processor_notify_smm() to consolidate error
handling in it and improve the comments in there while at it.

No expected functional impact.

Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>

Rearrange acpi_processor_unregister_performance() to follow a more
common error handling pattern and drop a redundant "return" statement
from the end of it.

No expected functional impact.

Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>

Drop some redundant parentheses and rearrange some checks using them
in the ACPI processor performance library code for better code clarity.

No expected functional impact.

Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>

Some inconsistent usage of white space in the ACPI processor performance
library code causes that code to be somewhat harder to read that it
would have been otherwise, so adjust the white space in there to
address that.

No expected functional impact.

Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>

Drop a redundant "else", a "return" statement at the end of a void
function and redundant parentheses around an unsigent int variable
name from the ACPI processor idle driver.

No expected functional impact.

Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>

It is not necessary to compare critical.flags.valid to 1 in
acpi_thermal_trips_update() and doing so is also inconsistent with
other similar checks in that code, so simply check if the flag is
not 0 instead.

No expected functional impact.

Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>

* pm-cpufreq:
  cpufreq: Remove CVS version control contents from documentation
  cpufreq: stats: Convert to use sysfs_emit_at() API

* acpi-fan:
  ACPI: fan: Convert to use sysfs_emit_at() API
  ACPI: fan: Bail out if extract package failed

Follow the advice of the Documentation/filesystems/sysfs.rst and show()
should only use sysfs_emit() or sysfs_emit_at() when formatting the
value to be returned to user space.

Signed-off-by: ye xingchen <ye.xingchen@zte.com.cn>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>

Since Linux moved to git, CVS is not relevant any more.

Signed-off-by: Conghui Wang <conghui.wang@hotmail.com>
[ rjw: Subject and changelog edits, dropped trailing spaces ]
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>

Follow the advice of the Documentation/filesystems/sysfs.rst and show()
should only use sysfs_emit() or sysfs_emit_at() when formatting the
value to be returned to user space.

Signed-off-by: ye xingchen <ye.xingchen@zte.com.cn>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>

* pm-cpufreq:
  cpufreq: ACPI: Only set boost MSRs on supported CPUs
  dt-bindings: cpufreq: cpufreq-qcom-hw: Add QDU1000/QRU1000 cpufreq
  cpufreq: tegra186: Use flexible array to simplify memory allocation
  cpufreq: apple-soc: Add new driver to control Apple SoC CPU P-states
  cpufreq: qcom-hw: Add CPU clock provider support
  dt-bindings: cpufreq: cpufreq-qcom-hw: Add cpufreq clock provider
  cpufreq: qcom-hw: Fix the frequency returned by cpufreq_driver->get()
  cpufreq: qcom-hw: Fix memory leak in qcom_cpufreq_hw_read_lut()
  arm64: dts: ti: k3-am625-sk: Add 1.4GHz OPP
  cpufreq: ti: Enable ti-cpufreq for ARCH_K3
  arm64: dts: ti: k3-am625: Introduce operating-points table
  cpufreq: dt-platdev: Blacklist ti,am625 SoC
  cpufreq: ti-cpufreq: Add support for AM625
  dt-bindings: cpufreq: qcom: Add missing cache related properties
  cpufreq: qcom-hw: Move soc_data to struct qcom_cpufreq
  cpufreq: qcom-hw: Use cached dev pointer in probe()
  cpufreq: qcom-hw: Allocate qcom_cpufreq_data during probe
  cpufreq: qcom-hw: Remove un-necessary cpumask_empty() check
  cpufreq: Generalize of_perf_domain_get_sharing_cpumask phandle format

Stop trying to set boost MSRs on CPUs that don't support boost.

This corrects a bug in the recent patch "Defer setting boost MSRs".

Fixes: 13fdbc8b ("cpufreq: ACPI: Defer setting boost MSRs")
Signed-off-by: Stuart Hayes <stuart.w.hayes@gmail.com>
Reported-by: Borislav Petkov (AMD) <bp@alien8.de>
Tested-by: Borislav Petkov (AMD) <bp@alien8.de>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>