- Mar 08, 2022
-
-
Thomas Huth authored
The new tests that have been added in commit bc0dd8bd ("x86/debug: Add single-step #DB + STI/MOVSS blocking tests") require a fixed kernel which we don't have in the Cirrus-CI yet, so let's disable the failing "debug" test for now. The "pcid" test has been renamed to "pcid-enabled" in commit cad94b13 ("x86: Add a 'pcid' group for the various PCID+INVPCID permutations"). Some additional tests are working fine now, too (pcid-asymmetric, msr, vmx_apic_passthrough_tpr_threshold_test, vmx_init_signal_test, vmx_pf_exception_test, vmx_sipi_signal_test), likely since the update to Fedora 35, so we can also enable them in the CI now. Message-Id: <20220308123538.538575-1-thuth@redhat.com> Signed-off-by:
Thomas Huth <thuth@redhat.com>
-
- Feb 17, 2022
-
-
Paolo Bonzini authored
s390x: smp lib improvements and more See merge request kvm-unit-tests/kvm-unit-tests!25
-
- Feb 16, 2022
-
-
Pierre Morel authored
Several tests are in need of a way to check on which hypervisor and virtualization level they are running on to be able to fence certain tests. This patch adds functions that return true if a vm is running under KVM, LPAR or generally as a level 2 guest. To check if we're running under KVM we use the STSI 3.2.2 instruction, let's define it's response structure in a central header. Signed-off-by:
Pierre Morel <pmorel@linux.ibm.com> Reviewed-by:
Janosch Frank <frankja@linux.ibm.com> Signed-off-by:
Claudio Imbrenda <imbrenda@linux.ibm.com>
-
Claudio Imbrenda authored
Adapt the test to the new semantics of the smp_* functions, and use CPU indexes instead of addresses. Signed-off-by:
Nico Boehr <nrb@linux.ibm.com> Reviewed-by:
Steffen Eiden <seiden@linux.ibm.com>
-
Claudio Imbrenda authored
Adapt the test to the new semantics of the smp_* functions, and use CPU indexes instead of addresses. replace the checks with asserts, the 3 CPUs are guaranteed to be there. Signed-off-by:
-
Claudio Imbrenda authored
Adapt the test to the new semantics of the smp_* functions, and use CPU indexes instead of addresses. Signed-off-by:
-
Claudio Imbrenda authored
Refactor all the smp_* functions to accept CPU indexes instead of CPU addresses. Add SIGP wrappers to use indexes instead of addresses. Raw SIGP calls using addresses are still possible. Some of the reworked functions also use the new wrappers internally, for clarity, even though that will cause unnecessary redundant checks on the validity of the CPU index. Add a few other useful functions to deal with CPU indexes. Signed-off-by:
-
Claudio Imbrenda authored
Guarantee that the boot CPU has index 0. This simplifies the implementation of tests that require multiple CPUs. Also fix a small bug in the allocation of the cpus array. Signed-off-by:
-
Claudio Imbrenda authored
If using the qemu CPU type, Protected Virtualization is not available, and the test will fail to start when run in PV. If specifying the host CPU type, the test will fail to start with TCG because the host CPU type requires KVM. In both cases the test will show up as failed. This patch adds a copy of the firq test definitions for KVM, using the host CPU type, and specifying that KVM is to be used. The existing firq tests are then fixed by specifying that TCG is to be used. When running the tests normally, both variants will be run. If an accelerator is specified explicitly when running the tests, only one variant will run and the other will be skipped (and not fail). Signed-off-by:
David Hildenbrand <david@redhat.com> Acked-by:
-
- Feb 14, 2022
-
-
Andrew Jones authored
Misc fixes See merge request kvm-unit-tests/kvm-unit-tests!24
-
The "linux,initrd-start" and "linux,initrd-end" properties encode the start and end address of the initrd. The size of the address is encoded in the root node #address-cells property and can be 1 cell (32 bits) or 2 cells (64 bits). Add support for parsing a 64 bit address. Signed-off-by:
Alexandru Elisei <alexandru.elisei@arm.com> [Fixed compilation for 32-bit arm with another cast.] Signed-off-by:
Andrew Jones <drjones@redhat.com>
-
Zhenzhong Duan authored
UEFI loads EFI applications to dynamic runtime addresses, so it requires all applications to be compiled as PIC (position independent code). The new introduced single-step #DB tests series bring some compile time absolute address, fixed it with RIP relative address. Fixes: 9734b423 ("x86/debug: Add framework for single-step #DB tests") Fixes: 6bfb9572 ("x86/debug: Test IN instead of RDMSR for single-step #DB emulation test") Fixes: bc0dd8bd ("x86/debug: Add single-step #DB + STI/MOVSS blocking tests") Signed-off-by:
Zhenzhong Duan <zhenzhong.duan@intel.com> Message-Id: <20220210092044.18808-1-zhenzhong.duan@intel.com> Signed-off-by:
Paolo Bonzini <pbonzini@redhat.com>
-
- Feb 09, 2022
-
-
Junming Liu authored
A split lock is any atomic operation whose operand crosses two cache lines. Since the operand spans two cache lines and the operation must be atomic, the system locks the bus while the CPU accesses the two cache lines. The bus lock operation is heavy weight and can cause severe performance degradation. Here's the log when run x86 test cases: [ 3572.765921] x86/split lock detection: #AC: qemu-system-x86/24383 took a split_lock trap at address: 0x400306 Root caused 'cpu_online_count' spans two cache lines, "lock incw cpu_online_count" instruction causes split lock. 'cpu_online_count' is the type of word(two bytes) and therefore it needs to be aligned to 2 bytes to avoid split lock. Signed-off-by:
Junming Liu <junming.liu@intel.com> Message-Id: <20220124111444.12548-1-junming.liu@intel.com> Signed-off-by:
-
Sean Christopherson authored
Explicitly set DR6.BS for the sub-test that verifies DR6.BS isn't cleared when a data breakpoint (a.k.a. H/W watchpoint) #DB occurs. Relying on the single-step #DB tests to leave DR6 is all kinds of mean. Signed-off-by:
Sean Christopherson <seanjc@google.com> Message-Id: <20220120002923.668708-8-seanjc@google.com> Reviewed-by:
Jim Mattson <jmattson@google.com> Signed-off-by:
-
Sean Christopherson authored
Add a variety of test cases to verify single-step #DB interaction with STI and MOVSS blocking. Of particular note are STI blocking and MOVSS blocking with DR7.GD=1, both of which require manual intervention from the hypervisor to set vmcs.GUEST_PENDING_DBG_EXCEPTION.BS when re-injecting an intercepted #DB with STI/MOVSS blocking active. Cc: David Woodhouse <dwmw2@infradead.org> Cc: Alexander Graf <graf@amazon.de> Signed-off-by:
-
Sean Christopherson authored
Clean up the mess that is debugreg.h to follow the nomenclature used by the SDM and the kernel (as best as possible). Use the "new" defines in various tests. Opportunistically add a define for VMX's extra flag in vmcs.GUEST_PENDING_DBG_EXCEPTIONS that is set if any DR0-3 trap matched and was enabled. No functional change intended. Signed-off-by:
-
Sean Christopherson authored
Run the single-step #DB tests in usermode in addition to running them in kernel mode, i.e. run at CPL0 and CPL3. Signed-off-by:
-
Sean Christopherson authored
Replace RDMSR with IN so that testing single-step #DBs on emulated instructions can be run in userspace (by modifying IOPL). IN is also more interesting in that it is guaranteed to exit to host userspace, whereas RDMSR will do so if and only if userspace is filtering the target MSR. Signed-off-by:
-
Sean Christopherson authored
Add a framework to the "debug" test for running single-step #DB tests, future commits will extend the single-step tests to run in usermode and to verify interaction with STI and MOVSS blocking. Opportunistically add comments and stop open coding RFLAGS stuff. No functional change intended. Signed-off-by:
-
Sean Christopherson authored
Include stdbool.h and stddef.h in bitops.h to pick up the definitions for "bool" and "size_t" respectively. Signed-off-by:
-
Aaron Lewis authored
Add a framework and test cases to ensure exceptions that occur in L2 are forwarded to the correct place by nested_vmx_reflect_vmexit(). Add testing for exceptions: #GP, #UD, #DE, #DB, #BP, and #AC. Signed-off-by:
Aaron Lewis <aaronlewis@google.com> Message-Id: <20220125203127.1161838-5-aaronlewis@google.com> Signed-off-by:
-
Aaron Lewis authored
Putting a vmcall() at the end of a nested test isn't always convenient to do, and isn't necessary. Add a helper to allow the nested test to make it possible to skip this requirement. Signed-off-by:
-
Aaron Lewis authored
KUT has a limit of only being able to run one nested guest per vmx test. This is limiting and not necessary. Add support for allowing a test to run guest code multiple times. Signed-off-by:
-
Aaron Lewis authored
exception_mnemonic() is a useful function for more than just desc.c. Make it global, so it can be used in other KUT tests. Signed-off-by:
-
Jim Mattson authored
Remove some inline assembly code duplication and opportunistically replace the magic constant, "0x10," with "MSR_IA32_TSC." Signed-off-by:
-
Jim Mattson authored
Opportunistically reorder the code to reduce indentation. Signed-off-by:
-
Jim Mattson authored
The subtest labeled, "MSR_IA32_TSC_ADJUST msr adjustment on tsc write," sometimes fails. The behavior tested is neither architected nor guaranteed. Running under qemu/kvm, the 'est_delta_time' has been observed to be as much as an order of magnitude greater than the expression that is supposed to be its upper bound. Remove the flaky subtest, and replace it with some invariants that actually are architecturally guaranteed (as long as IA32_TSC doesn't wrap around). Fixes: 5fecf5d8 ("Added tests for ia32_tsc_adjust funtionality.") Cc: Will Auld <will.auld.intel@gmail.com> Signed-off-by:
-
Andrew Jones authored
When compiling with an ancient compiler (gcc-4.8.5-36.el7_6.2.aarch64) the build fails with lib/libcflat.a(alloc.o): In function `mult_overflow': /home/drjones/kvm-unit-tests/lib/alloc.c:19: undefined reference to `__multi3' According to kernel commit fb8722735f50 ("arm64: support __int128 on gcc 5+") gcc older than 5 will emit __multi3 for __int128 multiplication. To fix this, let's just use check_mul_overflow(), which does overflow checking with GCC7.1+ and nothing for older gcc. We lose the fallback for older gcc, but oh, well, the heavily negative diffstat is just too tempting to go for another solution. While we're cleaning up lib/alloc.c with the function deletion also take the opportunity to clean up the include style and add an SPDX header. Reviewed-by:
-
- Feb 04, 2022
-
-
Janosch Frank authored
The specification and the kernel use UVC_CMD_PREPARE_RESET so let's fix our naming up. The call bit is named correctly but is not the same as the name we use on KVM. So let's clear that up too. Signed-off-by:
-
Christian Borntraeger authored
Until now we had multiple tests running under the same prefix. This can result in multiple identical lines like SKIP: cpumodel: dependency: facility 5 not present SKIP: cpumodel: dependency: facility 5 not present Make this unique by adding a proper prefix. Signed-off-by:
Christian Borntraeger <borntraeger@linux.ibm.com> Reviewed-by:
-
- Feb 01, 2022
-
-
Andrew Jones authored
arm64: Merge arm/queue See merge request kvm-unit-tests/kvm-unit-tests!23
-
Clang inlines some functions (like test_ss) which define global labels in inline assembly (e.g., ss_start). This results in: arm/debug.c:382:15: error: invalid symbol redefinition asm volatile("ss_start:\n" ^ <inline asm>:1:2: note: instantiated into assembly here ss_start: ^ 1 error generated. Fix these functions by marking them as "noinline". Cc: Andrew Jones <drjones@redhat.com> Signed-off-by:Ricardo Koller <ricarkol@google.com> Reviewed-by:
Oliver Upton <oupton@google.com> Signed-off-by:
-
Test the migration of single-step state. Setup single-stepping, migrate, and check that we are actually single-stepping. Signed-off-by:
-
Test the migration of watchpoint state. Program as many watchpoints as possible, migrate, and check that we get the corresponding exceptions. Signed-off-by:
-
Test the migration of breakpoint state. Program as many breakpoitns as possible, migrate, and check that we get the corresponding exceptions. Signed-off-by:
-
The TVAL test programs the timer to fire into the future, waits for an interrupt using the WFI instruction, and when the instruction completes it checks that the timer interrupt has fired. According to ARM DDI 0487G.a there are other wake-up events that can cause the WFI to complete (listed on page D1-2520), among them interrupts routed to a higher exception level, where the hypervisor is running (if running under virtualization) or firmware (if running on baremetal). In practice, this is unlikely to have caused a false test failure, because for a GICv3 (which the author assumes is a lot more common than a GICv4+) the WFI is trapped by KVM and the VCPU thread is resumed only after the timer asserts the interrupt, as the test expects. Signed-off-by:
-
The timer pending test uses CVAL to trigger changes in the timer interrupt state. Move the CVAL test before the pending test to make sure that writes to the CVAL register have an effect on the timer internal state before using the register for other tests. Signed-off-by:
-
At the moment, the timer test is one big function that checks different aspects of the timer implementation, and it's not immediately obvious if a check depends on a state from a previous test, making understanding the code more difficult than necessary. Move the checks into logically distinct functions and leave the timer in a known state before proceeding to the next test to make the code easier to understand, maintain and extend. The timer interrupt is now enabled at the GIC level in test_init() to break the dependency that the tests have on the timer pending test running first. There should be no functional change as a result of this patch. Signed-off-by:
-
ARM DDI 0487G.a states on page D13-4180 that, when the virtual timer is enabled, the timer condition is met when CNTVCT_EL0 - CNTV_CVAL_EL0 >= 0. Multiplying both sides of the inequality by -1, we get the equivalent condition CNTV_CVAL_EL0 - CNTVCT_EL0 <= 0 for when the timer should fire. On the same page, it states that a read of the CNTV_TVAL_EL0 register returns CNTV_CVAL_EL0 - CNTVCT_EL0 if the virtual timer is enabled. Putting the two together, the timer condition is met when the value of the TVAL register is less than or *equal* to 0. Same rules apply for the physical timer. Fix the check for the timer expiring by treating a TVAL value equal to zero as a valid condition for the timer to fire. Signed-off-by:
-
This will allow TCG tests to alter things such as tb-size. Signed-off-by:
Alex Bennée <alex.bennee@linaro.org> Message-Id: <20211202115352.951548-9-alex.bennee@linaro.org> Signed-off-by:
-
