Timer library for RISC-V.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>

Initial RISC-V Supervisor Mode trap handler.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>

This library provides CSR assembly functions to read/write RISC-V
specific Control and Status registers.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>

RISC-V processor package library definitions.

IndustryStandard/RiscV.h
-Add RiscV.h which conform with RISC-V Privilege Spec v1.10.

RiscVImpl.h
-Definition of EDK2 RISC-V implementation.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>

Fix input param error checking for the BcmGenetDxe ComponentName2
protocol.

This fixes https://github.com/pftf/RPi4/issues/85



Signed-off-by: Samer El-Haj-Mahmoud <samer.el-haj-mahmoud@arm.com>
Reviewed-by: Pete Batard <pete@akeo.ie>

Fix input param error checking for the DwUsbHostDxe ComponentName2
protocol.

This fixes https://github.com/pftf/RPi4/issues/86



Signed-off-by: Samer El-Haj-Mahmoud <samer.el-haj-mahmoud@arm.com>
Reviewed-by: Pete Batard <pete@akeo.ie>

Fix input param error checking for the DisplayDxe ComponentName2
protocol.

This fixes https://github.com/pftf/RPi4/issues/84



Signed-off-by: Samer El-Haj-Mahmoud <samer.el-haj-mahmoud@arm.com>
Reviewed-by: Pete Batard <pete@akeo.ie>

Any DSC file that uses the UefiCpuPkg MpInitLib or CpuExeptionHandlerLib
libraries, now requires the VmgExitLib library. Update the DSC files to
include the VmgExitLib NULL library implementation.

Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>

The UART namespace reference in DBG2 is incorrect. Fix to point to the
correct name.

This fixes the certification failure reported by FWTS tests at:
https://github.com/pftf/RPi4/issues/69



Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Pete Batard <pete@akeo.ie>
Cc: Andrei Warkentin <awarkentin@vmware.com>
Cc: Ard Biesheuvel <ard.biesheuvel@arm.com>
Signed-off-by: Samer El-Haj-Mahmoud <samer.el-haj-mahmoud@arm.com>
Reviewed-by: Pete Batard <pete@akeo.ie>

Set the supported RPi3 platform language to English (US),
and remove French.

This fixes https://github.com/pftf/RPi4/issues/35



Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Pete Batard <pete@akeo.ie>
Cc: Andrei Warkentin <awarkentin@vmware.com>
Cc: Ard Biesheuvel <ard.biesheuvel@arm.com>
Signed-off-by: Samer El-Haj-Mahmoud <samer.el-haj-mahmoud@arm.com>
Reviewed-by: Pete Batard <pete@akeo.ie>

Set the supported RPi4 platform language to English (US),
and remove French.

This fixes https://github.com/pftf/RPi4/issues/35



Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Pete Batard <pete@akeo.ie>
Cc: Andrei Warkentin <awarkentin@vmware.com>
Cc: Ard Biesheuvel <ard.biesheuvel@arm.com>
Signed-off-by: Samer El-Haj-Mahmoud <samer.el-haj-mahmoud@arm.com>
Reviewed-by: Pete Batard <pete@akeo.ie>
Reviewed-by: Andrei Warkentin <awarkentin@vmware.com>

Arm SBSA specification section ver 6.0, 4.1.5 defines specific PPI
values for certain standard interrupt IDs. The value for
"Performance Monitors Interrupt" needs to be 23.

REF: https://developer.arm.com/documentation/den0029/latest

This partially fixes SBSA test #11 ("Incorrect PPI value") reported in
https://github.com/pftf/RPi4/issues/74



Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Pete Batard <pete@akeo.ie>
Cc: Andrei Warkentin <awarkentin@vmware.com>
Cc: Ard Biesheuvel <ard.biesheuvel@arm.com>
Signed-off-by: Samer El-Haj-Mahmoud <samer.el-haj-mahmoud@arm.com>
Reviewed-by: Pete Batard <pete@akeo.ie>

GOP SetMode() returns the frame buffer size in FrameBufferSize.
The value is obtained from the RPi mailbox call to AllocateBuffer
(tag RPI_MBOX_ALLOC_FB), which for a native resolution of 1920 x 1080
returns 8355840 bytes. The size should be 1920 x 1080 x 4 (bytes/pixel),
or 8294400 bytes, as defined by the UEFI Spec: "FrameBufferSize :
Amount of frame buffer needed to support the active mode as defined by
PixelsPerScanLine x VerticalResolution x PixelElementSize".

This change forces the returned FrameBufferSize to match the value
required by UEFI Spec. The actual buffer allocted by the VPU is larger
due to the alignment request when calling RPI_MBOX_ALLOC_FB
(32 bytes). A vertical resolution of 1080 aligns to 1088 on 32-bytes,
resulting in the increased buffer size (1920 x 1088 x 4 = 8355840).

This fixes the SetMode_Conf failure reported by SCT tests at
https://github.com/pftf/RPi4/issues/73



Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Pete Batard <pete@akeo.ie>
Cc: Andrei Warkentin <awarkentin@vmware.com>
Cc: Ard Biesheuvel <ard.biesheuvel@arm.com>
Signed-off-by: Samer El-Haj-Mahmoud <samer.el-haj-mahmoud@arm.com>
Reviewed-by: Andrei Warkentin <awarkentin@vmware.com>

Return correct values of PixelInformation in QueryMode().

This fixes the QueryMode_Func failures reported by SCT tests at
https://github.com/pftf/RPi4/issues/73



Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Pete Batard <pete@akeo.ie>
Cc: Andrei Warkentin <awarkentin@vmware.com>
Cc: Ard Biesheuvel <ard.biesheuvel@arm.com>
Signed-off-by: Samer El-Haj-Mahmoud <samer.el-haj-mahmoud@arm.com>
Reviewed-by: Andrei Warkentin <awarkentin@vmware.com>

Handle incorrect parameters passed to DisplayDxe GOP functions
QueryMode(), SetMode(), and Blt().

This fixes Blt_Conf and QueryMode_Conf failures
reported by SCT tests at:
https://github.com/pftf/RPi4/issues/73



Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Pete Batard <pete@akeo.ie>
Cc: Andrei Warkentin <awarkentin@vmware.com>
Cc: Ard Biesheuvel <ard.biesheuvel@arm.com>
Signed-off-by: Samer El-Haj-Mahmoud <samer.el-haj-mahmoud@arm.com>
Reviewed-by: Andrei Warkentin <awarkentin@vmware.com>

Minor code cleanup:
 - Update file header to list SBBR required/recommended tables
 - Rename DataSmbiosHande to DataSmbiosHandle
 - Remove SMBIOS_HANDLE_PI_RESERVED from Type 11 template for
   consistency. This is already done in LogSmbiosData().

Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Pete Batard <pete@akeo.ie>
Cc: Andrei Warkentin <awarkentin@vmware.com>
Cc: Ard Biesheuvel <ard.biesheuvel@arm.com>
Signed-off-by: Samer El-Haj-Mahmoud <samer.el-haj-mahmoud@arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@arm.com>

Various fixes and enhancements for SMBIOS memory structures
(Types 16, 17, and 19):

 - Type 16:
    - Update MaximumCapacity dynamically
    - Keep ExtendedMaximumCapacity at 0 (not used, per spec)

 - Type 17:
   - Update Size and VolatileSize dynamically
   - Change FormFactor from Unknown to Chip
   - Set DeviceSet to 0 (not part of set) instead of 0xFF (unknown)
   - Fix the DeviceLocator, BankLocator, and Manufacturer strings
   - Update MemoryType correctly for RPi4 and RPi3
   - Add additional SMBIOS fields from 3.3 definition

 - Type 19:
   - Update MemoryArrayHandle to point to Type 16 handle

Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Pete Batard <pete@akeo.ie>
Cc: Andrei Warkentin <awarkentin@vmware.com>
Cc: Ard Biesheuvel <ard.biesheuvel@arm.com>
Signed-off-by: Samer El-Haj-Mahmoud <samer.el-haj-mahmoud@arm.com>
Reviewed-by: Andrei Warkentin <awarkentin@vmware.com>

Various fixes and enhancements for SMBIOS Type 7:
 - Break into 3 instances (L1 Instruction, L1 Data, and L2 cache)
 - Use correct values for RPi4 and RPi3 SoCs
 - Add Type 4 association with type 7 handles

Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Pete Batard <pete@akeo.ie>
Cc: Andrei Warkentin <awarkentin@vmware.com>
Cc: Ard Biesheuvel <ard.biesheuvel@arm.com>
Signed-off-by: Samer El-Haj-Mahmoud <samer.el-haj-mahmoud@arm.com>
Reviewed-by: Andrei Warkentin <awarkentin@vmware.com>

Various fixes and enhancements for SMBIOS Type 4:
 - Fix ProcessorId to correctly report the Arm64 MIDR_EL1 value
 - Change ProcessorUpgrade from Other to None
 - Add comments for ProcessorCharacteristics fields
 - Add CoreCount2, EnabledCoreCount2, and ThreadCount2
 - Set LxCacheHandle to 0xFFFF

Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Pete Batard <pete@akeo.ie>
Cc: Andrei Warkentin <awarkentin@vmware.com>
Cc: Ard Biesheuvel <ard.biesheuvel@arm.com>
Signed-off-by: Samer El-Haj-Mahmoud <samer.el-haj-mahmoud@arm.com>
Reviewed-by: Andrei Warkentin <awarkentin@vmware.com>

Various fixes and enhancements for SMBIOS Type 0:
 - Use PCDs to report the BIOS Segment and Size
 - Report Extended BiosSize
 - Set BiosIsUpgradable (it is!)
 - Clear FunctionKeyNetworkBootIsSupported

Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Pete Batard <pete@akeo.ie>
Cc: Andrei Warkentin <awarkentin@vmware.com>
Cc: Ard Biesheuvel <ard.biesheuvel@arm.com>
Signed-off-by: Samer El-Haj-Mahmoud <samer.el-haj-mahmoud@arm.com>
Reviewed-by: Andrei Warkentin <awarkentin@vmware.com>

Various fixes for SMBIOS Types 2 and 3:
 - Add LocationInChassis string to Type 2
 - Update Type 3 NumberofPowerCords to 1
 - Add ChassisHandle refernce to Type2. This requires moving the
   Type 3 population to happen before Type 2

Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Pete Batard <pete@akeo.ie>
Cc: Andrei Warkentin <awarkentin@vmware.com>
Cc: Ard Biesheuvel <ard.biesheuvel@arm.com>
Signed-off-by: Samer El-Haj-Mahmoud <samer.el-haj-mahmoud@arm.com>
Reviewed-by: Andrei Warkentin <awarkentin@vmware.com>

Commit 6d4fed69 added support for
reporting AssetTag in RPi SMBIOS Types 2 and 3. The default
AssetTag is an empty string. SMBIOS does not allow empty strings to be
referenced from the corresponding string field. This caused breakage in
parsing SMBIOS Types 2 and 3 fields that follow the AssetTag field.

The issue caused an FWTS test failure, as reported in:
https://github.com/pftf/RPi4/issues/75



The fix is to detect if no AssetTag is set in the UEFI variable, and if
so, change the AssetTag SMBIOS field to an empty blank space.

Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Pete Batard <pete@akeo.ie>
Cc: Andrei Warkentin <awarkentin@vmware.com>
Cc: Ard Biesheuvel <ard.biesheuvel@arm.com>
Signed-off-by: Samer El-Haj-Mahmoud <samer.el-haj-mahmoud@arm.com>
Reviewed-by: Andrei Warkentin <awarkentin@vmware.com>

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2401



Looks like Addresswidth is BIT wise values.
Right now these values are not used any.

Suggested-by: Star Zeng <star.zeng@intel.com>
Signed-off-by: Lorena R De Leon Vasquez <lorena.r.de.leon.vasquez@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>

For DXE_RUNTIME_DRIVER runtime safe version of DebugLib should be
used. Otherwise, any DEBUG print in code can result in abort in OS.

Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>

By default, gcc allows void* pointer arithmetic.
This is a GCC extension.
However, the C reference manual states that void*
pointer "cannot be operands of addition or subtraction
operators". Cf s5.3.1 "Generic Pointers".

This patch adds casts to avoid doing void* pointer arithmetic.

Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>

By default, gcc allows void* pointer arithmetic.
This is a GCC extension.
However, the C reference manual states that void*
pointer "cannot be operands of addition or subtraction
operators". Cf s5.3.1 "Generic Pointers".

This patch adds casts to avoid doing void* pointer arithmetic.

Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>

By default, gcc allows void* pointer arithmetic.
This is a GCC extension.
However, the C reference manual states that void*
pointer "cannot be operands of addition or subtraction
operators". Cf s5.3.1 "Generic Pointers".

This patch adds casts to avoid doing void* pointer arithmetic.

Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>

According to the bug:
https://bugzilla.tianocore.org/show_bug.cgi?id=2777


the deprecated code under DISABLE_NEW_DEPRECATED_INTERFACES
will be removed, which will result in compilation breakage
of the Marvell platforms. Prevent that by switching to the
different PcdSet API.

Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>

According to the bug:
https://bugzilla.tianocore.org/show_bug.cgi?id=2777


the deprecated code under DISABLE_NEW_DEPRECATED_INTERFACES
will be removed, which will result in compilation breakage
of the Raspberry Pi platforms. Prevent that by switching to
the different PcdSet API.

Signed-off-by: Pete Batard <pete@akeo.ie>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>

Per SMBIOS specs, The Type 0 BIOS Release Date is not a free form field but
must be specified in a US middle-endian format (mm/dd/yyyy), so make sure
we populate it accordingly by using the recently introduced TimeBaseLib
macros. This is required for platforms like Windows, that fail to parse the
date otherwise.

Also, the system manufacturer should not be set to the same value as the
board manufacturer for the Type 1 strings, as, on the Raspberry Pi, this is
not representative of the actual manufacturer of the system, which is the
Raspberry Pi Foundation always.

Signed-off-by: Pete Batard <pete@akeo.ie>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>

Add 'Yuwei Chen' as a reviewer for
Edk2-platforms\Platform\Intel\Tools and
Edk2-platforms\Silicon\Intel\Tools.

Cc: Liming Gao <liming.gao@intel.com>
Cc: Bob Feng <bob.c.feng@intel.com>
Signed-off-by: Yuwei Chen <yuwei.chen@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2777


With some functions to be deprecated, their usage in platforms
should also be updated.

Cc: Agyeman Prince <prince.agyeman@intel.com>
Signed-off-by: Shenglei Zhang <shenglei.zhang@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>

All of line endings of Acpi.dsc.inc are not CRLF, resolve this.

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>

The second SPI controller is wired to the low speed 96boards
connector on Developerbox. SynQuacer platform can exposes
its SPI TPM via MMIO window that is backed by the SPI
command sequencer in the SPI bus controller.
This commit adds the MMIO TPM description to the DSDT.

If TPM2_ENABLE build option is not enabled, existing linux
SPI driver is used instead of MMIO TPM.

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>

Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/ has both an Emmc.asl
and an Emmc.c file, which the patch(edk2 commit:0a4aa20e8d446 "BaseTools:
Compile AML bytecode arrays into .obj file") both generate an Emmc.obj
in the same output directory.

To fix the build error for Developerbox platform, this patch renames
the Emmc.c.

Suggested-by: Leif Lindholm <leif@nuviainc.com>
Cc: Pierre Gondois <Pierre.Gondois@arm.com>
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>

Include Silicon/ARM directory under ARM section entry.

Cc: Ard Biesheuvel <ard.biesheuvel@arm.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Signed-off-by: Pranav Madhu <Pranav.Madhu@arm.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
Reviewed-by: Thomas Abraham <thomas.abraham@arm.com>

Neoverse N1 System Development Platform (N1SDP) is an infrastructure
segment development platform. It includes a Neoverse N1 SoC and an
IOFPGA that provides access to low-bandwidth peripherals. It
also enables development of CCIX-enabled FPGA accelerators.

Cc: Ard Biesheuvel <ard.biesheuvel@arm.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
Reviewed-by: Thomas Abraham <thomas.abraham@arm.com>

Neoverse N1 SoC includes a PCIe root complex to which a AHCI, GbE and
USB controllers are attached as an endpoint. So implement the
PciHostBridgeLib glue layer and enable support for PCIe controller and
all the devices connected over the PCIe bus.

Cc: Ard Biesheuvel <ard.biesheuvel@arm.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
Reviewed-by: Thomas Abraham <thomas.abraham@arm.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>

A slave error is generated when host accesses the config space of
non-available device or unimplemented function on a given bus. So
implement a Neoverse N1 SoC specific PciExpressLib library with a
workaround to return 0xffffffff for all such access.

This library is inherited from MdePkg/Library/BasePciExpressLib and
based on commit 9344f0921518 of that library in the tianocore/edk2
project.

In addition to this, the Neoverse N1 SoC has two other limitations which
affect the access to the PCIe root port:
  1. ECAM space is not contiguous, root port ECAM (BDF = 0:0:0) is
     isolated from rest of the downstream hierarchy ECAM space.
  2. Root port ECAM space is not capable of 8bit/16bit writes.
This library includes workaround for these limitations as well.

Cc: Ard Biesheuvel <ard.biesheuvel@arm.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
Reviewed-by: Thomas Abraham <thomas.abraham@arm.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>

Add the initial Arm's Neoverse N1 System-on-Chip platform library
support. This includes the virtual memory map and helper functions for
platform initialization.

Cc: Ard Biesheuvel <ard.biesheuvel@arm.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
Reviewed-by: Thomas Abraham <thomas.abraham@arm.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>