- May 23, 2020
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Radoslaw Biernacki authored
The QEMU sbsa-ref platform provides an SBSA-compliant platform, providing EL3/EL2 support, non-virtio interfaces, etc. This patch adds initial support for this platform. We are using FDF to compose EFI flash images with TF-A images. Flash0 (secure) is used by BL1 and FIP (BL2 + BL31). Flash1 contains EFI code and EFI variables. Signed-off-by:
Tanmay Jagdale <tanmay.jagdale@linaro.org> Reviewed-by:
Leif Lindholm <leif@nuviainc.com>
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- May 20, 2020
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Ming Huang authored
There are some boards base on D06, but use RX8900 RTC, so upstream the RX8900RealTimeClockLib. Signed-off-by:
Ming Huang <huangming23@huawei.com> Reviewed-by:
Leif Lindholm <leif@nuviainc.com>
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Ming Huang authored
The functions of acquiring ownership of RTC will be used for other RTC library, so move them to RtcHelperLib. Rename them by add leading Oem for uniform. Signed-off-by:
Ming Huang <huangming23@huawei.com> Reviewed-by:
Leif Lindholm <leif@nuviainc.com>
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Ming Huang authored
There is a typo issue in M41T83RealTimeClockLib. The MACROSECOND should be MICROSECOND. Signed-off-by:
Ming Huang <huangming23@huawei.com> Reviewed-by:
Leif Lindholm <leif@nuviainc.com>
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- May 19, 2020
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Marcin Wojtas authored
If UTMI connected to USB Device, the MUX must be configured prior to the PHY init. Add missing register update in the relevant code. Signed-off-by:
Marcin Wojtas <mw@semihalf.com> Reviewed-by:
Leif Lindholm <leif@nuviainc.com>
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Marcin Wojtas authored
According to Design Reference Specification the PHY PLL and Calibration register from PHY0 are shared for multi-port PHY. PLL control registers inside other PHY channels are not used. This fixes issues in scenarios when only UTMI port1 was in use, which resulted with lack of correct PLL initialization. On the occasion add relevant comments, describing the register groups in the header file. Based on original change from Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by:
Marcin Wojtas <mw@semihalf.com> Reviewed-by:
Leif Lindholm <leif@nuviainc.com>
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Marcin Wojtas authored
This patch introduce following modifications, allowing to overcome the instabilities observed with certain USB2.0 endpoints: * Add additional step which enables the Impedance and PLL calibration. * Enable old squelch detector instead of the new analog squelch detector circuit and update host disconnect threshold value. * Update LS TX driver strength coarse and fine adjustment values. Based on original change from Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by:
Marcin Wojtas <mw@semihalf.com> Reviewed-by:
Leif Lindholm <leif@nuviainc.com>
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Ard Biesheuvel authored
Operator precedence is funny in DEPEX expressions, so let's add some parentheses to make it self explanatory. The resulting truth value is the same. Signed-off-by:
Ard Biesheuvel <ard.biesheuvel@arm.com> Reviewed-by:
Leif Lindholm <leif@nuviainc.com>
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Nate DeSimone authored
"beggining" should be "beginning" Signed-off-by:
Nate DeSimone <nathaniel.l.desimone@intel.com> Reviewed-by:
Leif Lindholm <leif@nuviainc.com> Cc: Marcin Wojtas <mw@semihalf.com> Cc: Leif Lindholm <leif@nuviainc.com>
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Ard Biesheuvel authored
Instead of unconditionally delaying the boot up to 5 seconds, even if no network cable is connected in the first place, provide an implementation of the EFI adapter information protocol so that the upper networking layers can wait gracefully for the link to come up, but only when the network is actually used to boot from. Signed-off-by:
Ard Biesheuvel <ard.biesheuvel@arm.com> Reviewed-by:
Leif Lindholm <leif@nuviainc.com>
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Ard Biesheuvel authored
The device path protocol is no longer installed by the NetSec driver, but by the platform driver. So drop it from the .INF. Signed-off-by:
Ard Biesheuvel <ard.biesheuvel@arm.com> Reviewed-by:
Leif Lindholm <leif@nuviainc.com>
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Ard Biesheuvel authored
The 96boards I2C driver currently relies on the platform to connect all controllers, or I2C peripherals will not be exposed if they are not the active boot target. Since I2C peripherals are not boot targets in the first place, but are used to expose things like random number generators, let's connect the I2C controllers specifically at EndOfDxe so that the devices living on it will be available regardless of the boot policy. Signed-off-by:
Ard Biesheuvel <ard.biesheuvel@arm.com> Reviewed-by:
Leif Lindholm <leif@nuviainc.com>
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Ard Biesheuvel authored
Drop the description of the interrupt handling part of the GPIO controller, and use a ACPI0013 Generic Event device instead to handle the power button event. This way, an OS can handle these events without the need for a SoC specific driver. Signed-off-by:
Ard Biesheuvel <ard.biesheuvel@arm.com> Reviewed-by:
Leif Lindholm <leif@nuviainc.com>
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- May 18, 2020
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Tan, Ming authored
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2710 It is used to support the Serial Port Console Redirection Table (SPCR). Signed-off-by:
Ming Tan <ming.tan@intel.com> Reviewed-by:
Eric Dong <eric.dong@intel.com>
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Dong, Eric authored
Signed-off-by:
Eric Dong <eric.dong@intel.com> Reviewed-by:
Chasel Chiu <chasel.chiu@intel.com> Reviewed-by:
Nate DeSimone <nathaniel.l.desimone@intel.com> Reviewed-by:
Liming Gao <liming.gao@intel.com>
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- May 15, 2020
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Pankaj Bansal authored
Add PEI phase to LS1043aRdb. This is needed because we need to have dynamic PCDs support to be able to reserve memory before reporting memory to UEFI firmware. Using PEI phase we are now also dynamically setting the PcdSystemMemoryBase and PcdSystemMemorySize depending upon the DRAM regions detected. This in turn would depend on the DDR DIMMs installed on board. Signed-off-by:
Pankaj Bansal <pankaj.bansal@nxp.com> Reviewed-by:
Leif Lindholm <leif@nuviainc.com>
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Pankaj Bansal authored
MemoryInitPeiLib would be linked to MemoryInitPeim, when we implement PEI phase. therefore, move the library to directory of same name. Signed-off-by:
Pankaj Bansal <pankaj.bansal@nxp.com> Reviewed-by:
Leif Lindholm <leif@nuviainc.com>
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Pankaj Bansal authored
Add VarStore Fd. This Fd is used to store non volatile variables in flash. Signed-off-by:
Pankaj Bansal <pankaj.bansal@nxp.com> Reviewed-by:
Leif Lindholm <leif@nuviainc.com>
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Pankaj Bansal authored
FVRules.fdf.inc is being replaced by the ArmVirtPkg/ArmVirtRules.fdf.inc at commit hash 746c5b6238f1ee55deb4b3ec32a6d732e27eeeaa Signed-off-by:
Pankaj Bansal <pankaj.bansal@nxp.com> Reviewed-by:
Leif Lindholm <leif@nuviainc.com>
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Pankaj Bansal authored
ArmPlatformHelper.S is being replaced by the ArmPlatformPkg version at commit hash f4dfad05dda2c7b29e8105605621f2b413f0af2b. Signed-off-by:
Pankaj Bansal <pankaj.bansal@nxp.com> Reviewed-by:
Leif Lindholm <leif@nuviainc.com>
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Pankaj Bansal authored
SocInit can be defined in SocLib.h No need to make it extern in ArmPlatformLib Signed-off-by:
Pankaj Bansal <pankaj.bansal@nxp.com> Reviewed-by:
Leif Lindholm <leif@nuviainc.com>
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Pankaj Bansal authored
The SocLib contains code specific to an Soc. it should be part of SOC package. Therefore, move the SocLib to Soc Package. Since we are moving the files to Soc Package, no need to mention the Soc name in file names. Their location is enough to indicate for which Soc the files are. Signed-off-by:
Pankaj Bansal <pankaj.bansal@nxp.com> Reviewed-by:
Leif Lindholm <leif@nuviainc.com>
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Pankaj Bansal authored
Now the we have added Chassis Package, move the chassis specific common code for all SOCs belonging to same chassis to ChassisLib. Use ChassisLib APIs in SocLib. Signed-off-by:
Pankaj Bansal <pankaj.bansal@nxp.com> Reviewed-by:
Leif Lindholm <leif@nuviainc.com>
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Pankaj Bansal authored
A Chassis is a base framework used for building SoCs. We can think of Chassis/Soc/Platform(a.k.a Board) in Object model terms. Chassis is base. Soc is based on some Chassis. Platform is based on some Soc. SOCs that are designed around same chassis, reuse most of the components. Therefore, add the package for Chassis2. LS1043A and LS1046A SOCs belong to Chassis2. Signed-off-by:
Pankaj Bansal <pankaj.bansal@nxp.com> Reviewed-by:
Leif Lindholm <leif@nuviainc.com>
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Pankaj Bansal authored
The SwapMmio** APIs are supposed to be called indirectly via GetMmioOperations** APIs. Therefore, remove the SwapMmio** APIs from IoAccessLib.h and make these APIs STATIC to IoAccessLib.c, so that no accidental call can be made to these. Signed-off-by:
Pankaj Bansal <pankaj.bansal@nxp.com> Reviewed-by:
Leif Lindholm <leif@nuviainc.com>
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Pankaj Bansal authored
Use NXP_PLATFORM_GET_CLOCK_PPI in various Layerscape IP modules. Signed-off-by:
Pankaj Bansal <pankaj.bansal@nxp.com> Reviewed-by:
Leif Lindholm <leif@nuviainc.com>
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Pankaj Bansal authored
The SOC takes primary clocking input from the external signal (a clock generator on board). The input (frequency) is multiplied using multiple phase locked loops (PLL) to create a variety of frequencies which can then be passed to a variety of internal logic, including cores and peripheral IP modules. Therefore, move the clock retrieval APIs to Platform Lib. The Input clock is retrieved from board components in Platform Lib, and passed on to SOC Lib APIs to get the correct clock for an IP (after PLL multiplication). Signed-off-by:
Pankaj Bansal <pankaj.bansal@nxp.com> Reviewed-by:
Leif Lindholm <leif@nuviainc.com>
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Pankaj Bansal authored
RAM retrieval using SMC commands is common to all Layerscape SOCs. Therefore, move it to common MemoryInit Pei Lib. Signed-off-by:
Pankaj Bansal <pankaj.bansal@nxp.com> Reviewed-by:
Leif Lindholm <leif@nuviainc.com>
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- May 14, 2020
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Kathappan Esakkithevar authored
The Ddr4MixedUDimm2DpcLimit FSP-M Upd has been renamed as Ddr4Mixed2DpcLimit at CometLakeFspBinPkg\CometLake1. FSP wrapper driver need to use FSP-M Upd name Ddr4Mixed2DpcLimit from CometLake1 FSP at CometlakeOpenBoardPkg. REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2714 Signed-off-by:
Kathappan Esakkithevar <kathappan.esakkithevar@intel.com> Cc: Sai Chaganty <rangasai.v.chaganty@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Deepika Kethi Reddy <deepika.kethi.reddy@intel.com> Reviewed-by:
Chasel Chiu <chasel.chiu@intel.com> Reviewed-by:
Sai Chaganty <rangasai.v.chaganty@intel.com> Reviewed-by:
Eric Dong <eric.dong@intel.com>
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- May 12, 2020
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Andrei Warkentin authored
TFTP and HTTP downloads were failing. The problem was that the incorrect PROD index was being written TX ring. The PROD index should be the TxProdIndex (in the range [0-0xffff]), not the descriptor index (in the range [0-num descs)). Also, mod 0xffff is not the same as & 0xffff, so fix that as well. Signed-off-by:
Andrei Warkentin <andrey.warkentin@gmail.com> Tested-by:
Samer El-Haj-Mahmoud <Samer.El-Haj-Mahmoud@arm.com>
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Ard Biesheuvel authored
The Raspberry Pi4 has gigabit ethernet builtin, for which we now have a UEFI driver. So no need for the ASIX 88772b driver. Signed-off-by:
Ard Biesheuvel <ard.biesheuvel@arm.com> Reviewed-by:
Andrei Warkentin <andrey.warkentin@gmail.com> Reviewed-by:
Samer El-Haj-Mahmoud <Samer.El-Haj-Mahmoud@arm.com> Reviewed-by:
Leif Lindholm <leif@nuviainc.com>
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Andrei Warkentin authored
Remove the PlatformPcdLib. It is completely unnecessary. Originally, this was meant for the GENET driver, but now that ConfigDxe registers the platform device, the library is superfluous. Signed-off-by:
Ard Biesheuvel <ard.biesheuvel@arm.com> Reviewed-by:
Leif Lindholm <leif@nuviainc.com>
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Ard Biesheuvel authored
Register an event at EndOfDxe to instantiate the EFI device path protocol with the GENET MAC address on a new handle, and install the BcmGenetPlatformDeviceProtocol on that handle. This protocol is used to pass platform information (GENET MAC address and register base address) to the GENET driver, which will consume this in its implementation of the UEFI driver model Supported/Start/Stop methods. Co-authored-by:
Samer El-Haj-Mahmoud <samer.el-haj-mahmoud@arm.com> Co-authored-by:
Ard Biesheuvel <ard.biesheuvel@arm.com> Co-authored-by:
Andrei Warkentin <awarkentin@vmware.com> Signed-off-by:
Ard Biesheuvel <ard.biesheuvel@arm.com> Reviewed-by:
Leif Lindholm <leif@nuviainc.com>
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Ard Biesheuvel authored
Do some preliminary cosmetic cleanup on ConfigDxe before making actual changes in a subsequent patch. Co-authored-by:
Samer El-Haj-Mahmoud <samer.el-haj-mahmoud@arm.com> Co-authored-by:
Ard Biesheuvel <ard.biesheuvel@arm.com> Co-authored-by:
Andrei Warkentin <awarkentin@vmware.com> Signed-off-by:
Ard Biesheuvel <ard.biesheuvel@arm.com> Reviewed-by:
Leif Lindholm <leif@nuviainc.com>
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Ard Biesheuvel authored
Move PCDs from GENET driver to Raspberry Pi and Bcm27xx packages. The Genet driver follows the UEFI driver model, so it should not have PCDs defined that describe MMIO and MAC addresses of a single instance. Also, move related definitions around, and update references accordingly. Signed-off-by:
Ard Biesheuvel <ard.biesheuvel@arm.com> Reviewed-by:
Leif Lindholm <leif@nuviainc.com>
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Ard Biesheuvel authored
Add support for the Broadcom GENET v5 ethernet controller for the Raspberry Pi 4 (BCM2711) Co-authored-by:
Jared McNeill <jmcneill@invisible.ca> Co-authored-by:
Andrei Warkentin <awarkentin@vmware.com> Co-authored-by:
Samer El-Haj-Mahmoud <samer.el-haj-mahmoud@arm.com> Co-authored-by:
Ard Biesheuvel <ard.biesheuvel@arm.com> Signed-off-by:
Ard Biesheuvel <ard.biesheuvel@arm.com> Reviewed-by:
Leif Lindholm <leif@nuviainc.com>
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Ard Biesheuvel authored
Add BcmGenetPlatformDevice definition for GENET. This protocol will be used to register GENET platform device that is on a non-discoverable bus. Signed-off-by:
Ard Biesheuvel <ard.biesheuvel@arm.com> Reviewed-by:
Leif Lindholm <leif@nuviainc.com>
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Ard Biesheuvel authored
The driver for the Broadcom Genet network controller will shortly be modified from a minimal MAC address programming driver to a true SNP driver implementing full network functionality. Since this will involve DMA, set the DmaLib parameters correctly in the platform. Signed-off-by:
Ard Biesheuvel <ard.biesheuvel@arm.com> Reviewed-by:
Leif Lindholm <leif@nuviainc.com>
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- May 11, 2020
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Andrei Warkentin authored
The scaled resolutions are useful, but are not the default expected by most users. Linux and BSDs don't set preferred resolution in their OS loader, so when booting via setup UI, the OS is left running at 800x600, not the native resolution. This looks crummy. Signed-off-by:
Andrei Warkentin <andrey.warkentin@gmail.com> Reviewed-by:
Pete Batard <pete@akeo.ie> Tested-by:
Pete Batard <pete@akeo.ie>
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Andrei Warkentin authored
Today the Pies can be booted in a way where only ACPI is exposed, or both ACPI and DT are exposed. This adds one more mode - DT only, no ACPI. The target audience is developers. When both are exposed, it's up to the OS to decide which gets used, and that choice can differ between OSes, Note: this does _not_ change defaults. Pi 3 still defaults to ACPI + DT, while Pi 4 still defaults to ACPI only. We don't really want to remove DT + ACPI mode - it is the default on Pi 3, and removing it is bound to just annoy users - WoA and NetBSD (voa UEFI) on Pi 3 only work with ACPI, while everything else (Linux, FreeBSD) only work with DT. I'd make an analogy of MPS and ACPI being exposed for the longest time ever together on PCs. Testing: OpenBSD on Pi 4 with DT-only and ACPI-only boots. Signed-off-by:
Andrei Warkentin <andrey.warkentin@gmail.com> Reviewed-by:
Pete Batard <pete@akeo.ie>
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