- Mar 04, 2025
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Rename RELEASES.md to CHANGELOG.md to be compatible with GitLab Change-Id: Icbb152e6213efd8bf53082cc48cd3d8dea5a4a68 Signed-off-by:
Rickard Bolin <rickard.bolin@arm.com>
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- Mar 03, 2025
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Tim Hall authored
- Issue was that networks with multiple inputs or outputs with tensors of different ranks could not be written out as a single NumPy array due to not having homogeneous shapes - Only affects Ethos-U55 and Ethos-U65 - The fix was to convert all raw output shapes to rank 4 Change-Id: Id5b2908e6a3332037c7833078c8d39de3094be72 Signed-off-by:
Tim Hall <tim.hall@arm.com>
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- Feb 28, 2025
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William Isaksson authored
Updates DEBUG_DB.md to reflect recent changes in the database Change-Id: I790692514aaf2eada0b32492716f9c73e267267e Signed-off-by:
William Isaksson <william.isaksson@arm.com>
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- Feb 27, 2025
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Tim Hall authored
- Fixed bug in selection of raw output - Aligned the raw output format Change-Id: Ia9de278afd4d972b04722abddca1a90fd0e9536b Signed-off-by:
Tim Hall <tim.hall@arm.com>
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Tim Hall authored
- Change the default TOSA behaviour for Ethos-U55/65 to use the Regor compilation core instead of the Python one Change-Id: I325b2f827e84f239dfe6de662dce588fe552c869 Signed-off-by:
Tim Hall <tim.hall@arm.com>
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Tim Hall authored
- Added a CLI option --list-configs to list the configurations defined in the specified config file Change-Id: I9a7ffa37d1367e568762aab119d47cf4a9448c40 Signed-off-by:
Tim Hall <tim.hall@arm.com>
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- Simplified README file and moved information to other docs - Created new BUILD.md to explain the manual build options Change-Id: I1c834257056e9cc1f11c8257316332e3c6c88379 Signed-off-by:
Rickard Bolin <rickard.bolin@arm.com>
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- Feb 26, 2025
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* Add option (--separate-io-regions) to put NPU input and output tensors in their own separate regions. * The tensors in the IO region are allocated with LinearAllocator so the memory used by inputs and outputs are not reused. * Add option (--cop-format) to use COP2 driver actions format. Change-Id: Ia564e4fec17abefa848161805b956d33a77f852d Signed-off-by:
Johan Gunnarsson <johan.gunnarsson@arm.com>
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- Feb 25, 2025
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- Issue was unordered_map being used but not included Change-Id: I7bb5a8d2583d12f5fb9e8691053b19e41738225f Signed-off-by:
Tim Hall <tim.hall@arm.com>
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Johan Gunnarsson authored
QuantizedScale can give us shifts in the range of [0, 63] but RoundingDivideByPOT can only handle shifts in the range of [0, 31], so try to move it into the smaller range before calling that function. Signed-off-by:
Johan Gunnarsson <johan.gunnarsson@arm.com> Change-Id: I24e8b67a28550bb88c0a746add06484af1c240d1
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- Feb 24, 2025
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Tim Hall authored
- Changed deprecated names to new versions of the same Change-Id: Ie1d187f830bdab28c5906a1ca99f3c7070386f67 Signed-off-by:
Tim Hall <tim.hall@arm.com>
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Change-Id: I11956e2b98b5e1e68d4b7f819fc3e89bdd88725f Signed-off-by:
Jacob Bohlin <jacob.bohlin@arm.com>
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Rickard Bolin authored
PGP key out of date, replace with link to let users download the latest key themselves. Change-Id: Ic6160a7cff6d1f07e0624038584d7c4ab4939ef4 Signed-off-by:
Rickard Bolin <rickard.bolin@arm.com>
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- Feb 23, 2025
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Signed-off-by:
Johan Gunnarsson <johan.gunnarsson@arm.com> Change-Id: I95e9e2be8b38b65c41953603ba29ef82805852e6
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- Feb 21, 2025
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Johan Gunnarsson authored
IsConstant will return false when the size is 0. This will trigger the assert for networks without weights, such as networks with only pool ops. Signed-off-by:
Johan Gunnarsson <johan.gunnarsson@arm.com> Change-Id: Iaadeffd654a3817ccf8ada796f76300ee319e957
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- Feb 20, 2025
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Also includes: * Zero point fix for PadV2. * Fix OFM slices for paddings. * Added quantization to IFM of the MemoryCopys. Change-Id: I60cc1c2693d38709a42cb2614395aec241687a5d Signed-off-by:
Jacob Bohlin <jacob.bohlin@arm.com>
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- Feb 19, 2025
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Rickard Bolin authored
Incorrect shape used to calculate sizes when reshaping to 3D Change-Id: Ie8ddf8f7397ea68a1e4bcb0361b99a18b1235112 Signed-off-by:
Rickard Bolin <rickard.bolin@arm.com>
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Fredrik Svedberg authored
Only tensor storage shape was updated in rewrite, however the connection shape needs to be updated as well. Change-Id: I7adf5deb4d0041b92dc4be9a8395e87433b164db Signed-off-by:
Fredrik Svedberg <fredrik.svedberg@arm.com>
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Rickard Bolin authored
Add documentation of the allowed output formats Change-Id: Ibf2207e6acba61f98f93c35efbe31c948aaabc21 Signed-off-by:
Rickard Bolin <rickard.bolin@arm.com>
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- Feb 18, 2025
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Update SUPPORTED_OPS.md to include MIRROR_PAD, SELECT and SELECT_V2 for Ethos-U85. Change-Id: I15f8671c1034b0645cae377bb1dfc1fabcb17b33 Signed-off-by:
Rickard Bolin <rickard.bolin@arm.com>
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- Feb 17, 2025
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Rickard Bolin authored
--verbose-weights no longer displays NPU Weights Size Signed-off-by:
Rickard Bolin <rickard.bolin@arm.com> Change-Id: I117ae64a50e8bbe6d9564973e4ac026b5ac11aad
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Jacob Bohlin authored
* Generic solution to reshape to 3D and always pad in W-dimension was causing performance regressions due to limitations in utilizing NHCWB16 format. With this change the reshape solution is only used when necessary. * Also cleaned up the RewritePad function a bit and made it so MemoryCopy is always used for applying the padding regardless of NPU. Previously elementwise NOT was used for Ethos-U85. Change-Id: I813d04caa165da4eb9586d220a0ff1554bb07083 Signed-off-by:
Jacob Bohlin <jacob.bohlin@arm.com>
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Philip Hall authored
The HLC op's ifm list is better created by inserting the ifm's in the correct order; rather than asserting that the originating order was incorrect. Signed-off-by:
Philip Hall <philip.hall@arm.com> Change-Id: Idb737bd2418d921e94198a81a53d322365dae7e6
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Fredrik Svedberg authored
Fixed DCO checking for merge requests from forks. Change-Id: I94eadc5ef1287d1cc3cdd7680dfc8265bd5d137f Signed-off-by:
Fredrik Svedberg <fredrik.svedberg@arm.com>
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- Feb 13, 2025
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Johan Alfvén authored
- Added former fallback mechanism to replace ReduceSum with a 1x1 Conv2D operation when Rescale is not available Change-Id: I4b2a26a80fc2e6de3262217c29094532306417a5 Signed-off-by:
Johan Alfvén <johan.alfven@arm.com>
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- Empty quantizations are interpreted as unit-scales in RCS Do the same thing in SupportsFusedRescale Change-Id: Ia9becbd4db8746d29eb65ad9d5389171deffa99d Signed-off-by:
Alexander Bengtsson <Alexander.Bengtsson@arm.com>
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- MLBEDSW-9591: OpType::Passthrough Slices should not be moved to CPU-operations - MLBEDSW-10426: OpType::Tile The RCS-TILE lowering assumes unsliced IFM. Change-Id: I923a650fc3ab127b1ff7e2b4c18d0a692a666372 Signed-off-by:
Alexander Bengtsson <Alexander.Bengtsson@arm.com>
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Change-Id: Id9ee6c1e1a40cf68dbf050c4d94bb37754208468 Signed-off-by:
Alexander Bengtsson <Alexander.Bengtsson@arm.com>
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- Feb 12, 2025
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Philip Hall authored
- Pad and trim input shapes for Ethos-U55 transpose implementation to 4 axes. - Fix depth-slicing by using correct depths for NWHC ifm and ofm strides. Signed-off-by:
Philip Hall <philip.hall@arm.com> Change-Id: Ic9b6aeb259ce9249c402bdb1e4c1308929ce7995
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Fredrik Svedberg authored
Fixed dilation decomposition in height and width dimensions for CONV3D sub operations. Change-Id: Id3b232b6e2ea5fd5a49ebde2671ae99739e949d2 Signed-off-by:
Fredrik Svedberg <fredrik.svedberg@arm.com>
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Recent ordered map traversal checks showed CAST operator inserts its IFMs in permuted order. This rearranges the IFMs to match traversal order. Signed-off-by:
Philip Hall <philip.hall@arm.com> Change-Id: Id3c9b4b43a2afb7f9cfc757d99e26d224d3960e3
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- Feb 11, 2025
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- ReduceSum only supports unit scaling on the IFM, update architectureConstraints to account for this. Change-Id: If072b0f3c6d92b631c1d0cae71336e5293f7ab08 Signed-off-by:
Alexander Bengtsson <Alexander.Bengtsson@arm.com>
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- Maintain rounding when lowering ReduceSum. - Fix shape of intermediate tensor when ReduceSum is lowered to ReduceSum + Sub (shape should be inherited from the tensor connection) - Keep quantization on the ReduceSum when ReduceSum is lowered to Transpose + ReduceSum. Change-Id: I9653f3638bbda8fa287a3f8a32c4bd3abe4e79ae Signed-off-by:
Alexander Bengtsson <Alexander.Bengtsson@arm.com>
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Philip Hall authored
A recent update let NPU op tests continue past the Transpose/Reverse operator check, allowing it to fail on unrelated data type criteria. This prevented INT32 transposes from being compiled. This commit inverts the check back for an early return. Signed-off-by:
Philip Hall <philip.hall@arm.com> Change-Id: I404b71047aa401e4f70bb754dd9ac4f676d3d792
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- Feb 10, 2025
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Fredrik Svedberg authored
Added initial support for TOSA CONV3D. Change-Id: Id4de4a11da26a555f05941f08d8f176309fcefda Signed-off-by:
Fredrik Svedberg <fredrik.svedberg@arm.com>
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Jacob Bohlin authored
Avoid having separate handling of TFLite Pad now that GraphIR lowering supports all Ethos-U targets. TFLite graph optimiser will now convert TFLite Pad to TOSA Pad which is then target-dependetly lowered in GraphIR optimiser. Change-Id: Id133173173721556f85a4231184bc70018333fe2 Signed-off-by:
Jacob Bohlin <jacob.bohlin@arm.com>
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Update constraints query mechanism to allow the architecture to return additional requirements for executing operators (including allocating scratch tensors). - Added matmul handling stubs for Ethos-U55. - Fixed tflite Resize operator check. - Fixed missing Sigmoid/LUT conversion checks. - Fixed bisecting search failure test in graph builder. Signed-off-by:
Philip Hall <philip.hall@arm.com> Change-Id: I8a612f709cc2d846caf13ec8b18d309c4cc66753
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HLCS generation uses a positional equivalence between tensor index and tensor usage to map ifms from Schedule IR to HLCS. This doesn't scale and required looping over a fixed number of IFMs. - Switch from positional to tensor-usage based IFM mappings. - Allow potentially unlimited input IFMs for HLCS operators. - Improved field layout of HLCFeaturemap to reduce memory wasted by padding. Signed-off-by:
Philip Hall <philip.hall@arm.com> Change-Id: Iea517eb8994e70ba3d8c0618dfd487706e785b60
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- Feb 07, 2025
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Fredrik Svedberg authored
Updated contribution documentation with information about forks. Change-Id: I47c03c03aa2bf90013705941b6342b9dbb6207ef Signed-off-by:
Fredrik Svedberg <fredrik.svedberg@arm.com>
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Fredrik Svedberg authored
Added DCO check to CICD pipeline. Change-Id: I9eeec783935cc01725b2656aee7bc57a8696b864 Signed-off-by:
Fredrik Svedberg <fredrik.svedberg@arm.com>
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