Tony Nadackal authored Dec 13, 2022 and Tony Nadackal committed Dec 22, 2022

Few of the model parameters now have fixed value and so the model
run-script does not have to set them anymore. Accordingly, remove those
parameters from the model run-script.

Signed-off-by: Tony K Nadackal <tony.nadackal@arm.com>
Change-Id: I47b38f179aaf69cbca1d9266117469a00c808884

Sayanta Pattanayak authored Dec 14, 2022 and Tony Nadackal committed Dec 22, 2022

This patch enables CXL device and includes it as part of
model PCIe topology.

Signed-off-by: Sayanta Pattanayak <sayanta.pattanayak@arm.com>
Change-Id: Id9b0b40d4eb532b6be7f5cdaf4dbdbf224d9b7d1

Tony Nadackal authored Nov 23, 2021 and Tony Nadackal committed Dec 22, 2022

Add initial model startup support for RD-N2-Cfg3 platform. This
supports busybox, buildroot, distro boot, secure boot and acs tests.

Signed-off-by: Tony K Nadackal <tony.nadackal@arm.com>
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: Ic93f1eed0659b21133f89020c65e031f572543a5

Tony Nadackal authored Dec 01, 2022 and Tony Nadackal committed Dec 22, 2022

This reverts commit 0bbc1679.

Signed-off-by: Tony K Nadackal <tony.nadackal@arm.com>
Change-Id: I1537a3aa7908a3d912e3be239b353f47dd5d79f5

Nishant Sharma authored Sep 30, 2022 and Vivek Kumar Gautam committed Dec 22, 2022

Adding new topologies that add new devices for x4_0, x4_1, and x8 PCIe
root complexes. The topologies are configured to be in the same segment.
That means all the root complexes will have bus numbers and ECAM ranges
in continuation.

Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Change-Id: I322f5e6301dc0ca342bf05b3a58b0831facbab95

Enable model parameters for various DMA PL330 devices present on
RD-N2-Cfg2 platform to discover the devices from non-secure Linux
kernel.

Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
Change-Id: I0c025aa8457a9a37aeb6bf08ba6597b54e883d9e

Set the number of MHU channels for SCP to SCP communication required
to pass information about PCIe topology discovery.

Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
Change-Id: I12a2e51d45ca61a7fa434f5c6b1eaa17a6392c6b

Nishant Sharma authored Sep 02, 2022 and Vivek Kumar Gautam committed Dec 22, 2022

Enable default PCIe topology on all chips of RD-N2-Cfg2 plaform.

Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Change-Id: I3bbaba34a9cd1e41b92a9fe9486c9649a1a6e0da

Nishant Sharma authored Sep 01, 2022 and Vivek Kumar Gautam committed Dec 22, 2022

Update the PCIe example hierarchy files to use the correct bus numbers
and ecam addresses to work with the dynamic PCIe hierarchy discovery.

Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Change-Id: I3ccfb2c1b2043cdf4bdc5e272cc9c517b039f968

Shriram authored Sep 28, 2022 and Vijayenthiran Subramaniam committed Sep 28, 2022

Add support for executing tftf on rdv2 platform.

Signed-off-by: Shriram K <shriram.k@arm.com>
Change-Id: I8dfea53d41b7dc4f74c5517b207ebc61a5548f53

Rohit Mathew authored Sep 12, 2022 and Vijayenthiran Subramaniam committed Sep 27, 2022

Non-secure MPAM register 'hnf_mpam_idr' on read returns 0x1007F as the
default value. However, OS expects the value to be 0x4301007F where
'0x43' indicates support for hnf_mpam_has_ccap_part and
hnf_mpam_has_cpor_part. Add additional model parameter for RD-N2-Cfg1
reference design platform to append `0x43` to the default value
returned.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I059c58736091134206c737e9864d0f901e9dd0fb

Shriram authored Sep 10, 2022 and Vijayenthiran Subramaniam committed Sep 26, 2022

Update the quantum value from 500 to 480. This change is required to
support Trusted Firmware Test Framework on SGI-575 platform as quantum
value greater than 480 makes the test framework hang in-between the test
cases. The quantum parameter is one of the FVP parameters that is used
to adjust the timing precision of the FVP.

Signed-off-by: Shriram K <shriram.k@arm.com>
Change-Id: Iad1c924cadc4b75c4f67ad10a9f1e2f1336847b6

Shriram authored Aug 26, 2021 and Vijayenthiran Subramaniam committed Sep 26, 2022

Add support for executing tftf on rdn2cfg1 platform.

Signed-off-by: Shriram K <shriram.k@arm.com>
Change-Id: I85e98f463c1b528111524796a8bcd0ea1ffcbb0b

Shriram authored Aug 12, 2021 and Vijayenthiran Subramaniam committed Sep 26, 2022

Add support for executing tftf on rdn2 platform.

Signed-off-by: Shriram K <shriram.k@arm.com>
Change-Id: Iedbc46a729e733727cbe4f68525347e2f1c7149e

Shriram authored Aug 26, 2021 and Vijayenthiran Subramaniam committed Sep 26, 2022

Add support for executing tftf on rdv1 platform.

Signed-off-by: Shriram K <shriram.k@arm.com>
Change-Id: I5effbf98910519b334a82673b9cdc61017e1e8cb

Neoverse Reference Design platform RD-Edmunds has been renamed to RD-V2
and all corresponding references have been changed.

Signed-off-by: Joel Goddard <joel.goddard@arm.com>
Change-Id: I2c0c18265f306511cc6868e31908a3eb59b1c6d4

Add 'flow_ctrl_mask_en' and 'enable_dc4' parameters for the non-secure
console port. This is required to allow key inputs with WinPE.

Signed-off-by: Thomas Abraham <thomas.abraham@arm.com>
Change-Id: Id5925a8edd0815cee24125ea422b1594324cb6f6

Rohit Mathew authored Dec 13, 2021 and Thomas Abraham committed Mar 27, 2022

Rename uart output file name (the file used to capture the uart output)
and associated shell variables to match with the current uart
configuration.

TF-A boot, runtime and MM logs would be routed via secure port. The
file name and shell variable associated with this port are prefixed
accordingly. Likewise, uefi and OS logs would be routed via non-secure.
The file name and shell variable associated with this port are also
prefixed accordingly.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Ibbf2599153620c92759942f9b7e40012d1250232

Rohit Mathew authored Dec 13, 2021 and Thomas Abraham committed Mar 27, 2022

Use secure and non-secure uarts in CSS instead of the uarts in SOC.
TF-A boot, runtime and Standalone MM logs would be routed via
css[0/1/2/3].pl011_s_uart_ap (secure port). UEFI and OS logs would be
routed via css[0/1/2/3].pl011_ns_uart_ap (non-secure port)

Additionally, as TF-A and MM logs would be routed via the same UART
port, remove unused model parameters that are used for configuring uart
port for capturing Standalone MM logs.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I0e8fa6c1b8e143cf316471a719c668b39734ef11

Rohit Mathew authored Dec 13, 2021 and Thomas Abraham committed Mar 27, 2022

Use secure and non-secure uarts in CSS instead of the uarts in SOC.
TF-A boot, runtime and Standalone MM logs would be routed via
css.pl011_s_uart_ap (secure port). UEFI and OS logs would be routed
via css.pl011_ns_uart_ap (non-secure port)

Additionally, as TF-A and MM logs would be routed via the same UART
port, remove unused model parameters that are used for configuring uart
port for capturing Standalone MM logs.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I817290aa97d058e240c2712a1783932c37604f90

Rohit Mathew authored Dec 13, 2021 and Thomas Abraham committed Mar 27, 2022

Use secure and non-secure uarts in CSS instead of the uarts in SOC.
TF-A boot, runtime and Standalone MM logs would be routed via
css.pl011_s_uart_ap (secure port). UEFI and OS logs would be routed
via css.pl011_ns_uart_ap (non-secure port)

Additionally, as TF-A and MM logs would be routed via the same UART
port, remove unused model parameters that are used for configuring uart
port for capturing Standalone MM logs.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Iddf81d0e93497cbc64c0abe02d4a18c56735c0d2

Rohit Mathew authored Dec 13, 2021 and Thomas Abraham committed Mar 27, 2022

Use secure and non-secure uarts in CSS instead of the uarts in SOC.
TF-A boot, runtime and Standalone MM logs would be routed via
css.pl011_s_uart_ap (secure port). UEFI and OS logs would be routed
via css.pl011_ns_uart_ap (non-secure port)

Additionally, as TF-A and MM logs would be routed via the same UART
port, remove unused model parameters that are used for configuring uart
port for capturing Standalone MM logs.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I724e175ca23654e78369c556dd39f10c73b00c8d

Rohit Mathew authored Dec 12, 2021 and Thomas Abraham committed Mar 27, 2022

Use secure and non-secure uarts in CSS instead of the uarts in SOC.
TF-A boot, runtime and Standalone MM logs would be routed via
css[0/1/2/3].pl011_uart1_ap (secure port). UEFI and OS logs would be
routed via css[0/1/2/3].pl011_uart_ap (non-secure port)

Additionally, as TF-A and MM logs would be routed via the same UART
port, remove unused model parameters that are used for configuring uart
port for capturing Standalone MM logs.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I179b3a4c3c2e394b3c3814867fea11840306ace1

Rohit Mathew authored Dec 12, 2021 and Thomas Abraham committed Mar 27, 2022

Use secure and non-secure uarts in CSS instead of the uarts in SOC.
TF-A boot, runtime and Standalone MM logs would be routed via
css.pl011_uart1_ap (secure port). UEFI and OS logs would be routed via
css.pl011_uart_ap (non-secure port)

Additionally, as TF-A and MM logs would be routed via the same UART
port, remove unused model parameters that are used for configuring uart
port for capturing Standalone MM logs.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I2f413601a5b53fd33501183a9786e111dd9ab199

Rohit Mathew authored Dec 12, 2021 and Thomas Abraham committed Mar 27, 2022

Use secure and non-secure uarts in CSS instead of the uarts in SOC.
TF-A boot, runtime and Standalone MM logs would be routed via
css[0/1].pl011_uart1_ap (secure port). UEFI and OS logs would be routed
via css[0/1].pl011_uart_ap (non-secure port)

Additionally, as TF-A and MM logs would be routed via the same UART
port, remove unused model parameters that are used for configuring uart
port for capturing Standalone MM logs.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I5d3ba4ddaa6b980dbb6745ecb2b6d8042917bcb6

Rohit Mathew authored Dec 12, 2021 and Thomas Abraham committed Mar 27, 2022

Use secure and non-secure uarts in CSS instead of the uarts in SOC.
TF-A boot, runtime and Standalone MM logs would be routed via
css.pl011_uart1_ap (secure port). UEFI and OS logs would be routed via
css.pl011_uart_ap (non-secure port)

Additionally, as TF-A and MM logs would be routed via the same UART
port, remove unused model parameters that are used for configuring uart
port for capturing Standalone MM logs.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Ife044dd91c9308847f49082089ab7f85f7b8e3fc

Rohit Mathew authored Dec 12, 2021 and Thomas Abraham committed Mar 27, 2022

Use secure and non-secure uarts in CSS instead of the uarts in SOC.
TF-A boot, runtime and Standalone MM logs would be routed via
css.pl011_uart1_ap (secure port). UEFI and OS logs would be routed via
css.pl011_uart_ap (non-secure port)

Additionally, as TF-A and MM logs would be routed via the same UART
port, remove unused model parameters that are used for configuring uart
port for capturing Standalone MM logs.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Iba08f707912147970b4a6d39be9d20eae98e72c8

Rohit Mathew authored Dec 12, 2021 and Thomas Abraham committed Mar 27, 2022

Use secure and non-secure uarts in CSS instead of the uarts in SOC.
TF-A boot, runtime and Standalone MM logs would be routed via
css.pl011_uart1_ap (secure port). UEFI and OS logs would be routed via
css.pl011_uart_ap (non-secure port)

Additionally, as TF-A and MM logs would be routed via the same UART
port, remove unused model parameters that are used for configuring uart
port for capturing Standalone MM logs.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I9495b3d3a1852b87ac1c832ead5b64d917e828c6

Pranav Madhu authored Mar 10, 2022 and Thomas Abraham committed Mar 27, 2022

For supporting ACS SBSA compiance, and to support hotplug functionality,
it is required to improve the timing precisition of FVP. Add parameters
for the same.

Change-Id: Iec23af51ab376ee378ad12f9f6715dd5cb32d325
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>

The parameters used to launch the model is displayed when the model is
launched. There are redundant spaces displayed in the displayed model
parameters. Remove those redundant spaces.

Signed-off-by: Thomas Abraham <thomas.abraham@arm.com>
Change-Id: I3eeda07accdd88ee8e5444945f94ea4a993eee21

FVP_RD_N2_Multichip has been renamed to FVP_RD_N2_Cfg2 starting from
11.16/25 version. Update the warning message accordingly.

Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: Ie29daa30ec7c58609c00f65c230a32bf568513d0

RD-N2-Cfg2 platform has four TZCs (0-3) on each chip. Remove additional
four TZCs (4-7) that were programmed to bypass on each chip.

Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: I82459dd75b6a972baaf6811545823a2b884303dc

Shriram authored Nov 26, 2021 and Vijayenthiran Subramaniam committed Nov 26, 2021

Replace the term "u-root" with "busybox" in the comments since booting
of stage-2 kernel with busybox prompt is automated. Also update the
disclaimer message, since we no longer boot stage-1 linux kernel by
replacing the UEFI Shell binary.

Signed-off-by: Shriram K <shriram.k@arm.com>
Change-Id: I2a3126f127ad67aca6be6906881b4acd6761235f

FVP by default blocks all the transaction if trustzone controller (TZC)
is not configured by software. This is an opposite behaviour to hardware
which allows all access if the TZC is not configured by software. To
align with hardware behaviour, use model parameters to configure TZC to
be bypassed and allow all access until software reconfigures the TZC.

Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: Id8e4f5160df2655ee29fc182ba29b46fdd6e31e9

FVP by default blocks all the transaction if trustzone controller (TZC)
is not configured by software. This is an opposite behaviour to hardware
which allows all access if the TZC is not configured by software. To
align with hardware behaviour, use model parameters to configure TZC to
be bypassed and allow all access until software reconfigures the TZC.

Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: I4f5c22bce7fb1f6067c394db21b5329a439dd666

FVP by default blocks all the transaction if trustzone controller (TZC)
is not configured by software. This is an opposite behaviour to hardware
which allows all access if the TZC is not configured by software. To
align with hardware behaviour, use model parameters to configure TZC to
be bypassed and allow all access until software reconfigures the TZC.

Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: I6ee4dc2c45cca786ec178ec7403f3b161cd2417f

FVP by default blocks all the transaction if trustzone controller (TZC)
is not configured by software. This is an opposite behaviour to hardware
which allows all access if the TZC is not configured by software. To
align with hardware behaviour, use model parameters to configure TZC to
be bypassed and allow all access until software reconfigures the TZC.

Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: Icae0f6fe9ad9e48cdfa173a55b82e81d81b7e54c

FVP by default blocks all the transaction if trustzone controller (TZC)
is not configured by software. This is an opposite behaviour to hardware
which allows all access if the TZC is not configured by software. To
align with hardware behaviour, use model parameters to configure TZC to
be bypassed and allow all access until software reconfigures the TZC.

Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: I2ea2a29432b04b5fc9418f4480e97d6e266335b7

Until 11.15 version, RD-N2-Cfg2 FVP had `mem` component which
instantiated `n` number of TZC's statistically and controlled the access
to number of regions required for a particular TZC during runtime.
Starting from 11.16 version, the `mem` component is removed and the
number of regions parameter (`tzcN.num_region`) for a particular TZC has
been removed as a model parameter and is configured statically by the
model.

Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: I7def859a4ff1df1dc83f7a17e07086aa823737e4

Until 11.15 version, RD-Edmunds FVP had `mem` component which
instantiated `n` number of TZC's statistically and controlled the access
to number of regions required for a particular TZC during runtime.
Starting from 11.16 version, the `mem` component is removed and the
number of regions parameter (`tzcN.num_region`) for a particular TZC has
been removed as a model parameter and is configured statically by the
model.

Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: Id404803404ee2b834609b9ad9c395faf89b43c99