- Jun 17, 2025
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Paul Elliott authored
Rebase MR CY25Q1 5 See merge request !31 Notable changes from base repository: * Added arch guards to Intel specific code in imb_hash_burst_get_size implementation in capabilities.c. * Added arch guards to unsupported algorithms in capabilities.c * Added aarch64 specific Make and CMake adjustments to compile capabilities.c * Added arch guards to Intel specific code in imb_get_arch_type_string implementation in capabilities.c
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Signed-off-by:
Marcel Cornu <marcel.d.cornu@intel.com>
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Signed-off-by:
Marcel Cornu <marcel.d.cornu@intel.com>
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Signed-off-by:
Marcel Cornu <marcel.d.cornu@intel.com>
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- Rename function - Add correct digest offset name Signed-off-by:
Marcel Cornu <marcel.d.cornu@intel.com>
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This code change adds XSAVE feature detection and makes AVX architecture depend on it. Note that AVX2 and AVX512 architectures also depend on all AVX features and consequently depend on XSAVE feature, too.
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Signed-off-by:
Pablo de Lara <pablo.de.lara.guarch@intel.com>
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Signed-off-by:
Pablo de Lara <pablo.de.lara.guarch@intel.com>
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Function added to return if a AEAD algorithm is supported by the AEAD burst API. Signed-off-by:
Pablo de Lara <pablo.de.lara.guarch@intel.com>
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Function added to retrieve the minimum burst size to be used in the cipher-only burst API (IMB_SUBMIT_CIPHER_BURST) to get optimal performance, based on the implementation used. If a cipher algorithm is not supported, it returns an error. Signed-off-by:
Pablo de Lara <pablo.de.lara.guarch@intel.com>
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Signed-off-by:
Pablo de Lara <pablo.de.lara.guarch@intel.com>
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Signed-off-by:
Pablo de Lara <pablo.de.lara.guarch@intel.com>
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Signed-off-by:
Marcel Cornu <marcel.d.cornu@intel.com>
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Primary process randomizes name of shared memory region so that multiple instances of the test can run in parallel. Randomized names are passed on from the primary process to the secondary process as command line arguments.
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Extra messages added on system call errors.
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Signed-off-by:
Marcel Cornu <marcel.d.cornu@intel.com>
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Signed-off-by:
Marcel Cornu <marcel.d.cornu@intel.com>
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Signed-off-by:
Marcel Cornu <marcel.d.cornu@intel.com>
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Signed-off-by:
Pablo de Lara <pablo.de.lara.guarch@intel.com>
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Signed-off-by:
Pablo de Lara <pablo.de.lara.guarch@intel.com>
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Most algorithms implemented in this library has multiple implementations. To help understanding which implementation is used, a new field in IMB_MGR is added to store the architecture subtype, and a new API to retrieve the one selected (e.g. AVX512 Type 2). Signed-off-by:
Pablo de Lara <pablo.de.lara.guarch@intel.com>
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Signed-off-by:
Pablo de Lara <pablo.de.lara.guarch@intel.com>
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Function added to retrieve the minimum burst size to be used in the hash-only burst API (IMB_SUBMIT_HASH_BURST) to get optimal performance, based on the implementation used. If a hash algorithm is not supported, it returns an error. Signed-off-by:
Pablo de Lara <pablo.de.lara.guarch@intel.com>
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- Jun 06, 2025
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Paul Elliott authored
Rebase MR CY25Q1 4 See merge request !30 Notable changes from the base repository: * Several includes of intel-ipsec-mb.h have been renamed to ipsec-mb.h * mp test app has been excluded from aarch64 builds due to a segfault when running. mp gets removed from the Intel repo in the future so we do not need to include this.
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Signed-off-by:
Pablo de Lara <pablo.de.lara.guarch@intel.com>
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Signed-off-by:
Pablo de Lara <pablo.de.lara.guarch@intel.com>
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Signed-off-by:
Pablo de Lara <pablo.de.lara.guarch@intel.com>
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- fork() support on Windows is limited - split monolithic code into modules - move utility functions into separate header files (shared memory, shared memory allocations etc.) - split primary process application from the secondary one
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This is to help multi-process scenarios i.e. active-passive or fail over.
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At the moment, for certain data sizes, correct functionality relies on NOP (0x90) padding.
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SHA256/224 one block function wasn't preserving xmm7 on Windows. This function is used of IPAD/OPAD calculations in the self test.
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In some cases, original message text appeared again in the 2nd block of the message schedule.
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Signed-off-by:
Marcel Cornu <marcel.d.cornu@intel.com>
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Signed-off-by:
Marcel Cornu <marcel.d.cornu@intel.com>
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