- Mar 12, 2024
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Tom Cosgrove authored
Stub hmac_ipad_opad for aarch64 See merge request !22
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Jack Bond-Preston authored
This method isn't supported on AArch64, but needs to be stubbed to have an implementation, in order to maintain ABI compatibility with x86_64 ipsec-mb library. Change-Id: I662ca65ab33b7ad4e4e094571563e02b97d82fc3
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- Mar 05, 2024
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Fangming Fang authored
Use bits as snow3g offset See merge request !21
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Fangming Fang authored
Change-Id: I2dba5fdff48780af5d5eb814d6b88e9dc498e676
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- Oct 13, 2023
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Fangming Fang authored
Fix SNOW3G functional error on SVE256. See merge request !20
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- Oct 12, 2023
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Fisher Yu authored
Change-Id: I9a68c1df9adca8cc97a42426ee00d39ce65514d3
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- Sep 28, 2023
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Fangming Fang authored
Refine Makefiles in examples/ test/ and perf/ See merge request !19
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Fisher Yu authored
Use header and lib files in lib/ to build examples/ test/ and perf/, do not search header and lib files from /usr/include and /usr/lib . Change-Id: I728119f3654f742d5b2a2b5447d3d011296495ac
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- Sep 27, 2023
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Fangming Fang authored
Merge intel-ipsec-mb v1.4 into 'main' See merge request !18
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Fisher Yu authored
1. Merge files in lib/, test/, perf/, cmake/, docs/, examples/, and root dir with intel-ipsec-mb except docs/index.html. 2. Modify intel-ipsec-mb.h to ipsec-mb.h 3. Add "__aarch64__" macro to files in lib/ perf/ test/, to manage code for AARCH64. 4. Add crc32_aarch64.c to lib/aarch64 5. Modify "asm" to "__asm__" in lib/aarch to compat -std=c99. 6. Rename aesni_emu_aarch64.S, zuc_common.S, zuc_sbox.S to aesni_emu_aarch64.inc, zuc_common.inc, zuc_sbox.inc. 7. Add " CMAKE_SYSTEM_PROCESSOR STREQUAL "aarch64" " to some CMakeLists.txt to manage code for AARCH64. 8. Add "-Wno-unused-parameter -Wno-unused-variable -Wno-unused-function" to CFLAGS in Makefile and CMakeLists.txt. Change-Id: I2c668561fd045f7f3c288441e8449c9ff3f027a4
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- Aug 09, 2023
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Fangming Fang authored
Implement ZUC-EIA3, ZUC256-EEA3 and ZUC256-EIA3. See merge request !17
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- Aug 08, 2023
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Fisher Yu authored
Flollow changes in this patch. 1. implement ZUC_AUTH_4, which generates N*16 bytes keystream for 4 lanes, and calculates intermediate tag values. 2. Implement ZUC_AUTH256_4, which generates N*16 bytes keystream for 4 lanes, and calculates intermediate tag values. 3. Implement _zuc_eia3_4_buffer, which generates 4/8/16 bytes tags according to key_size and tag_size. 4. Implement IMB_ZUC256_EEA3_N_BUFFER and IMB_ZUC256_EIA3_N_BUFFER. 5. Modify message length limitaion in ipsec-mb.h, to follow "128-EEA3 and 128-EIA3 Specification" v1.8. 6. Add test cases for zuc256-EIA3, zuc256-EEA3. 7. Reuse code from zuc_aarch64_top.c to zuc_aarch64_no_aesni_top.c, to make the code easier to maintain. 8. Unify coding style of zuc_simd.S, use TAB in assembly file.
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- Jul 28, 2023
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Fangming Fang authored
Fix mb manager init, and optimize zuc assembly implementation. See merge request !16
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- Jul 27, 2023
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Fisher Yu authored
Follow changes in this patch. 1. assign vector registers to LFSR0-15, BRX0-3 and FR1-2, to reduce load&store. 2. modify alignment, remove useless constant data. 3. use instruction SLI to implement rotate. 4. use instruction BIC to clear MSB in MOD (2^31-1). 5. use instruction TRN1 to implement halfword swap in bits_reorg4. 6. remove useless instructions in S0_compute_NEON, MUL_TBL_NEON. 7. reorder instructions in nonlin_fun4, lfsr_updt4, bits_reorg4, MUL_TLB_NEON, S0_compute_NEON to eliminate dependency. 8. remove ADD W in work mode. Change-Id: I15f1afb57b0036a3e8aa2183dafd11d0fd28c8d2
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Fisher Yu authored
1. Use macros to point to submit/flush functions for different uarch, instead of using function pointers. 2. Move reset_ooo_mgr to mb_mgr_code_aarch64.h, to reduce duplicate code. Change-Id: I9d95cce82274d7da111c35d63fe5ee2b1485922d
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- Jul 20, 2023
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Fangming Fang authored
Add SVE to tested arch list of ipsec_xvalid.c See merge request !15
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- Jul 19, 2023
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Fisher Yu authored
Change-Id: Idb4ffa337e6a42b209fb12c8a66562886b772918
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- Jun 21, 2023
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Fangming Fang authored
Remove useless header file dependency in test files. See merge request !14
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Fangming Fang authored
Optimize SNOW3G implementation to fix compilation warnings. See merge request !13
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Fisher Yu authored
Change-Id: Ie6c5d5e658d46135beb943df237dc71e8e5585e4
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Fisher Yu authored
Change-Id: I1aecb252d29b3e1bac6cb2fd7fe3cc44c9d6741a
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- Jun 20, 2023
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Fangming Fang authored
Revert the version to v1.3 See merge request !12
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Fangming Fang authored
This is a workaround to fix compiling issue on Arm. The version of this repo is v1.4, but actually it's a development branch instead of the formal v1.4 branch. see: https://www.mail-archive.com/dev@dpdk.org/msg268556.html Change-Id: Icf31fc7f5d36da91a77f2474018b974eaeb0a0fd
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- Jun 06, 2023
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Pablo de Lara authored
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Pablo de Lara authored
If IMB_MGR is NULL, errno is set in global variable. If key parameter is NULL, but IMB_MGR is NULL, the errno is set inside IMB_MGR.
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Tomasz Kantecki authored
- perform all plain text loads before doing stores - without the workaround, on Intel Atom(R) processors, performance penalty may be observed in NOT 4-byte aligned address and an in-place operation
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Tomasz Kantecki authored
- add new include file for aes-cbc encrypt based algorithms - use macro from the new include file for aes-cbc encrypt, aes-cmac and aes-xcbc
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Pablo de Lara authored
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Marcel Cornu authored
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Marcel Cornu authored
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Marcel Cornu authored
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Pablo de Lara authored
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Pablo de Lara authored
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Pablo de Lara authored
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Marcel Cornu authored
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- Jun 02, 2023
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Kania, Iwo authored
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Marcel Cornu authored
Co-authored-by:
Tomasz Kantecki <tomasz.kantecki@intel.com>
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Marcel Cornu authored
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Marcel Cornu authored
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Marcel Cornu authored
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