- Aug 18, 2022
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RD-N2-Cfg2 platform contains a PCIe Root Bridge with SMMU in the path. To allow the OSPM to discover and enumerate, add Iort, Mcfg and Ssdt tables. Signed-off-by:
Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com> Change-Id: Ie876f5503cd1cc1c184e89436885c80b37e7804c
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- Aug 17, 2022
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RD-N2-Cfg2 platform contains one PCIe Root Bridge that support up to 128 buses. To enable support for PCI in RD-N2-Cfg2 platform, add PCDs related to PCI in its platform description file. Signed-off-by:
Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com> Change-Id: I2ce6538826b5b9d4296df6e62a47c80db307fdbc
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- Aug 16, 2022
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Add the no-stack-protector complier flag for both AArch64 and x86 host build of StandaloneMM. Signed-off-by:
Tony K Nadackal <tony.nadackal@arm.com> Change-Id: I2c546bf01d4b5bbdf4854c05e413c7c595c19e71
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EINJ ACPI table mandates at least one entry of trigger error action table be present. To suffice this add one instruction entry to trigger error action table. Also set the EINJ buffer memory region to 0. Change-Id: Idf2af8216ceb5aa4e6edc6eed9b502fc21e4f3cb Signed-off-by:
Omkar Anand Kulkarni <omkar.kulkarni@arm.com>
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- Aug 15, 2022
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Define PCD values for EINJ buffer. Add memory map entry for the EINJ buffer to allow OSPM to access the EINJ memory region. Signed-off-by:
Omkar Anand Kulkarni <omkar.kulkarni@arm.com> Change-Id: I1511d021eb176d76ebb51d2e93043ac7b285cc83
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Enable initial support for EINJ ACPI table for RdN2Cfg1 platform. EINJ table uses Gic Spi interrupt as a error injection trigger event. Signed-off-by:
Omkar Anand Kulkarni <omkar.kulkarni@arm.com> Change-Id: I1e7e1d4d43d6d3cd67515ced65109e171903075d
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Enable the use CPU MM driver on SGI/RD platforms. This allows firmware-first error handling and reporting of CPU's 1-bit CE and DE that happen on caches, TLB's and MMU. Signed-off-by:
Omkar Anand Kulkarni <omkar.kulkarni@arm.com> Change-Id: I814f3bf5bbb0a775820b0e668fd2d1ad833aba2d
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Support added for handling 1-bit CE and DE that occur on CPU's L1 & L2 caches, TLB and MMU. MMI handler is implemented that collects all the error information and notifies OS. The driver implements the HEST error source descriptor protocol in order to publish the GHESv2 type error source descriptor for single-bit DRAM errors. The GHESv2 error source descriptor that is published is of type 'ARM Processor Error'. The driver registers a MMI handler for handling 1-bit CE and DE errors. On error event, the TF-a collates all the error information including the error record registers, the context registers and invokes the MMI handler. Depending on the security state of the error, the handler populates ARM Processor Error Section information structure and returns. Signed-off-by:
Omkar Anand Kulkarni <omkar.kulkarni@arm.com> Change-Id: Id273b8bfa64ad107c7f08a4fdb9e9dc83a861b5d
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Enables firmware first error handling on the given platform. Installs and publishes the SDEI and HEST ACPI tables required for firmware first error handling. Signed-off-by:
Omkar Anand Kulkarni <omkar.kulkarni@arm.com> Change-Id: Ib8c97b3d091eff062e4298467425b4e290a91a43
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For ACPI tables that are generated dynamically, define the ACPI table header values that have to be used to build the table header. Co-authored-by:
Thomas Abraham <thomas.abraham@arm.com> Signed-off-by:
Omkar Anand Kulkarni <omkar.kulkarni@arm.com> Change-Id: I2704c91f61c1fb02987bdcecd7c6a5b9553d9a96
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Enable the use of HEST table generation protocol, GHES error source descriptor protocol on ARM Neoverse Reference Design platforms. This enables the framework to support firmware first error handling on ARM Neoverse Reference Design platforms. Co-authored-by:
Thomas Abraham <thomas.abraham@arm.com> Signed-off-by:
Omkar Anand Kulkarni <omkar.kulkarni@arm.com> Change-Id: Ie6fd56aca13042aaa65a959c53eedb55913d9cdd
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The RD-N2-Cfg1 platform uses one instance of the IO Virtualization block to connect PL011 UART controllers and PL330 DMA controllers. Describe these devices by including the SsdtIoVirtBlk.asl ACPI table. In addition to this, add named-component IORT nodes for DMA PL330 DMA controllers that is interfaced with the SMMUv3 present in the IO virtualization block that is used to connect non-discoverable devices. This node maps to the DMA PL330 device node present in Ssdt table for the platform. Signed-off-by:
Vivek Gautam <vivek.gautam@arm.com> Signed-off-by:
Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com> Change-Id: I97a76135338630e288b345de93af54c72fc5ddbc
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The RD-N2 platform uses one instance of the IO Virtualization block to connect PL011 UART controllers and PL330 DMA controllers. Describe these devices by including the SsdtIoVirtBlk.asl ACPI table. In addition to this, add named-component IORT nodes for DMA PL330 DMA controllers that is interfaced with the SMMUv3 present in the IO virtualization block that is used to connect non-discoverable devices. This node maps to the DMA PL330 device node present in Ssdt table for the platform. Signed-off-by:
Vivek Gautam <vivek.gautam@arm.com> Signed-off-by:
Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com> Change-Id: I2a9c73e949524c9f15bd18fca251101929181376
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For platform that connect non-discoverable devices to IO virtualization block, add a SSDT table to describe those devices. PL011 UART controller and PL330 DMA controller are connected to the non-discoverable IO virtualization block. Signed-off-by:
Vivek Gautam <vivek.gautam@arm.com> Signed-off-by:
Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com> Change-Id: Ie1501b13a51bb872cdcb8cc49dee0e11631a38b9
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The IO virtualization block on reference design platforms allow connecting non-discoverable devices such as PL011 UART. On platforms that support this, initialize the UART controller connected to the IO virtualization block. Signed-off-by:
Shriram K <shriram.k@arm.com> Change-Id: I70bd3f790f51fa86707b0d300b3a70168731a4ff
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The IO topology on the RD-N2-Cfg1 platform is built using the IO Virtualization block. There are two instances of the IO Virtualization block on the RD-N2 platform and one of these instances is used to connect to a PCIe root bridge. Add RD-N2-Cfg1 platform specific IORT, MCFG and SSDT ACPI tables to represent this IO topology. Signed-off-by:
Vivek Gautam <vivek.gautam@arm.com> Signed-off-by:
Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com> Change-Id: I73821600d58811c641f2bb5c2da0a492c94ee251
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The IO topology on the RD-N2 platform is built using the IO Virtualization block. There are five instances of the IO Virtualization block on the RD-N2 platform and four of these instances are used to connect to PCIe root bridge. Add RD-N2 platform specific IORT, MCFG and SSDT ACPI tables to represent this IO topology. Signed-off-by:
Vivek Gautam <vivek.gautam@arm.com> Signed-off-by:
Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com> Change-Id: I095114b2bb894b969af0b03aa330e046246f2562
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Add helper macros for generation of the MCFG, SSDT and IORT ACPI table. The macro EFI_ACPI_SMMUv3_ID_TABLE_INIT simplifies the addition of the SMMUv3 ID remapping table in the IORT table. The macro EFI_ACPI_PCI_RC_ECAM_INIT describes the location of the PCI Express configuration space in the MCFG ACPI table. The macro EFI_ACPI_PCI_RC_INIT simplifies the addition of the root complex entry in the SSDT ACPI table. Signed-off-by:
Vivek Gautam <vivek.gautam@arm.com> Signed-off-by:
Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com> Change-Id: Ic1b57cd1047d8940adc7909c33d57ffd728998f3
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In preparation of adding multiple SMMU, IORT and PCIe root complex nodes into the IORT ACPI table, parameterize the existing IORT table. The SMMU interrupt numbers, device ID and base addresses are all parameterized using helper macros. PCDs for these parameters are defined and the platforms can define the value of these PCDs. Signed-off-by:
Vivek Gautam <vivek.gautam@arm.com> Signed-off-by:
Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com> Change-Id: If631ad3695fb5c7a87c11906fa2331d328fd3495
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For reference design platforms that support more than one PCIe host bridge, update the PCIe host bridge library implementation to allow support for upto four PCIe host bridges. PCDs are introduced to allow platforms to specify the values for bus count and the various MMIO base address and sizes. The available PCIe resources are split equally between the various host bridge instances in the system and macros have been introduced that makes it easier to implment this split. Signed-off-by:
Vivek Gautam <vivek.gautam@arm.com> Signed-off-by:
Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com> Change-Id: I974f07f6442e85ce9dea9730bb3be4c955551965
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- Aug 09, 2022
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Isolated CPUs are those that are not to be used on the platform for various reasons. The isolated CPU list is an array of MPID values of the CPUs that have to be isolated. This list is supplied via the NT_FW_CONFIG dtb. Add support to search for isolated CPUs MPID list and, if present, update the MADT table to disable the corresponding CPUs. Signed-off-by:
Nishant Sharma <nishant.sharma@arm.com> Change-Id: I9f7af896c1bcf0e0845b8b4f9f2bc199f15e6cc2
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Add a new device entry in the SSDT ACPI table to describe the serial port used as the debug port. On the Neoverse reference design platforms, the UART0 port of the SoC is used as the debug port. Signed-off-by:
Rohit Mathew <rohit.mathew@arm.com> Change-Id: I6f75f79e86b93609b7b83d1ada1e2693593cb5f7
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Patch 433b5b1b ("Platform/Sgi: Route logs to different sets of consoles") assigns different address for the console UART and the debug UART. Correspondingly, update the SPCR and SSDT ACPI tables to use the address of the console UART port instead of the debug UART port. Signed-off-by:
Rohit Mathew <rohit.mathew@arm.com> Change-Id: I93ef75ba4f7a2f3fbd35072ef6b4b18e0714c90b
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- Aug 08, 2022
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Ankit Sinha authored
Add mapping for all enabled and disabled threads in MADT Cc: Isaac Oram <isaac.w.oram@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Eric Dong <eric.dong@intel.com> Signed-off-by:
Ankit Sinha <ankit.sinha@intel.com> Reviewed-by:
Isaac Oram <isaac.w.oram@intel.com>
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Benjamin Doron authored
The DXE and SMM versions of AcpiDebug perform the same task and are therefore mutually exclusive. Including both modules results in a duplicate ACPI table, resulting in the feature not working at all. Therefore, add a new PCD to determine which module will be included. Now, either version successfully write to the debug buffer. Cc: Sai Chaganty <rangasai.v.chaganty@intel.com> Cc: Isaac Oram <isaac.w.oram@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Ankit Sinha <ankit.sinha@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Eric Dong <eric.dong@intel.com> Signed-off-by:
Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-by:
Isaac Oram <isaac.w.oram@intel.com>
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Guo Dong authored
UefiPayloadPkg in EDK2 repo was added SMM variable support for Intel platform with SPI flash. But some of the modules for SMM variable are Intel PCH specific (e.g. SPI library, SMM PCH module), so move these modules into edk2-platforms repo. A platform payload FV could be built from PlatformPayloadPkg which works on Intel platforms (e.g.. ICX, APL, CML, CFL, KBL, TGL, ADL, etc.) with SMM variable. This platform payload FV could be added into universal UEFI payload built from EDK2 UefiPayloadPkg. The steps to build a complete payload (use windows host as example): set WORKSPACE=c:\payload set PACKAGES_PATH=C:\payload\edk2;C:\payload\edk2-platforms\Platform\Intel; C:\payload\edk2-platforms\Features\Intel; edk2\edksetup.bat python edk2\UefiPayloadPkg\UniversalPayloadBuild.py -t VS2019 -D SMM_SUPPORT=TRUE -DVARIABLE_SUPPORT=NONE python edk2-platforms\Features\Intel\PlatformPayloadPkg\PlatformPayloadPkg.py -t VS2019 -D SMM_VARIABLE=TRUE -s The final UEFI payload generated at Build\UefiPayloadPkgX64\UniversalPayload.elf if build success. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Sean Rhodes <sean@starlabs.systems> Signed-off-by:
Guo Dong <guo.dong@intel.com> Signed-off-by:
Isaac Oram <isaac.w.oram@intel.com> Reviewed-by:
Sai Chaganty <rangasai.v.chaganty@intel.com>
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Michael Kubacki authored
The data buffer returned from the GetVariable2() call in TestPointCheckMemoryTypeInformation() is not actually used or freed. This change removes the unnecessary function call. Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Isaac Oram <isaac.w.oram@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Eric Dong <eric.dong@intel.com> Signed-off-by:
Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by:
Isaac Oram <isaac.w.oram@intel.com>
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Michael Kubacki authored
DumpMemoryTypeInfoSummary() is used to dump information about the MemoryTypeInformation HOB. The dump function currently modifies the data which can corrupt the data for later HOB consumers in the DXE phase. This change makes DumpMemoryTypeInfoSummary() treat the data as read-only. Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Isaac Oram <isaac.w.oram@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Eric Dong <eric.dong@intel.com> Signed-off-by:
Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by:
Isaac Oram <isaac.w.oram@intel.com>
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- Aug 07, 2022
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Pedro Falcato authored
Check its alignment and value for possible bad values. Cc: Marvin Häuser <mhaeuser@posteo.de> Signed-off-by:
Pedro Falcato <pedro.falcato@gmail.com> Reviewed-by:
Marvin Häuser <mhaeuser@posteo.de>
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- Aug 06, 2022
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Savva Mitrofanov authored
This changes tends to improve security of code sections by fixing integer overflows, missing alignment checks, unsafe casts, also simplified some routines, fixed compiler warnings and corrected some code mistakes. - Set HoleLen to UINT64 to prevent truncation in Ext4Read function - Replace EXT4_BLOCK_NR with 32-bit EXT2_BLOCK_NR in BlockMap, because by specification files using block maps must be placed within the first 2^32 blocks of a filesystem - Replace UNREACHABLE with ASSERT (FALSE) in case of new checksum algorithms, due to it is an invariant violation rather than unreachable path - Solve compiler warnings. Initialize all fields in gExt4BindingProtocol Fix comparison of integer expressions of different signedness - Field name_len has type CHAR8, while filename limit is 255 (EXT4_NAME_MAX), so because structure EXT4_DIR_ENTRY would be unchangeable in future, we could drop this check without any assertions - Simplify Ext4RemoveDentry logic by using IsNodeInList - Fix possible int overflow in Ext4ExtentsMapKeyCompare - Return bad block type in Ext4GetBlockpath - Adds 4-byte aligned check for superblock group descriptor size field Cc: Marvin Häuser <mhaeuser@posteo.de> Cc: Pedro Falcato <pedro.falcato@gmail.com> Cc: Vitaly Cheptsov <vit9696@protonmail.com> Signed-off-by:
Savva Mitrofanov <savvamtr@gmail.com> Reviewed-by:
Marvin Häuser <mhaeuser@posteo.de> Reviewed-by:
Pedro Falcato <pedro.falcato@gmail.com>
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- Aug 03, 2022
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Ankit Sinha authored
1. Add the PCD for GPE 1 block register width control in FADT 2. Re-arrange PCD category for some PCDs Cc: Isaac Oram <isaac.w.oram@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Eric Dong <eric.dong@intel.com> Signed-off-by:
Ankit Sinha <ankit.sinha@intel.com> Reviewed-by:
Isaac Oram <isaac.w.oram@intel.com>
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KalaiyarasanX Thangaraj authored
VirtualKeyboardFeaturePkg: Pre OS virtual keyboard touch response are very slow with I2C touch panel On one Touch, multiple Reads happend and this reads varying based on Key Press time. Resulting in Multiple key press update on screen. This condition avoids KeyPressed skips resulting due to faster key press and update only on valid key press. Cc: Dandan Bi <dandan.bi@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Madhan Pethaiyan <madhan.pethaiyan@intel.com> Cc: Kathappan Esakkithevar <kathappan.esakkithevar@intel.com> Cc: Madhusudhan Balaji <madhusudhan.balaji@intel.com> Signed-off-by:
KalaiyarasanX Thangaraj <kalaiyarasanx.thangaraj@intel.com> Reviewed-by:
Balaji, Madhusudhan <madhusudhan.balaji@intel.com> Reviewed-by:
Dandan Bi <dandan.bi@intel.com>
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- Aug 02, 2022
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Dimitrije Pavlov authored
Commit 6eb407947592e084110a124be089bef167af1383 added a new dependency of PlatformPKProtectionLib to SecureBootVariableLib. This causes the build of SbsaQemu to fail. Add the PlatformPKProtectionLib library instance to SbsaQemu.dsc to fix the build. Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jeff Booher-Kaeding <Jeff.Booher-Kaeding@arm.com> Cc: Samer El-Haj-Mahmoud <Samer.El-Haj-Mahmoud@arm.com> Signed-off-by:
Dimitrije Pavlov <Dimitrije.Pavlov@arm.com>
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- Aug 01, 2022
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Dimitrije Pavlov authored
Arm SBBR specification includes the list of required and recommended SMBIOS tables. Tables of types 16 (Physical Memory Array), 17 (Memory Device), and 19 (Memory Array Mapped Address) are required, but are not included in the current SbsaQemu SMBIOS driver. The current SMBIOS driver provides a limited number of tables using ArmPkg. This patch adds SbsaQemu-specific tables of types 16, 17, and 19. Signed-off-by:
Dimitrije Pavlov <Dimitrije.Pavlov@arm.com> Reviewed-By:
Samer El-Haj-Mahmoud <Samer.El-Haj-Mahmoud@arm.com> Reviewed-by:
Sunny Wang <sunny.wang@arm.com>
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- Jul 31, 2022
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Sami Mujawar authored
The definition for ARM_PROCESSOR_TABLE has been removed by commit c8af26627a4e9a3659255dc147d75596da08248e as it is a pseudo ACPI table. This causes the JadePkg builds to fail. Therefore, update Ampere/JadePkg to reflect this change. Signed-off-by:
Sami Mujawar <sami.mujawar@arm.com> Reviewed-by:
Ard Biesheuvel <ardb@kernel.org>
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- Jul 29, 2022
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Sami Mujawar authored
The edk2 patch at 103fa647d159e3d76be2634d2653c2d215dd0d46 updated the ARM_CORE_INFO structure to remove the ClusterId and CoreId fields in the ARM_CORE_INFO structure in favor of a new Mpidr field. Therefore, fix the ArmPlatformLibrary instance for Platform/NXP/LX2160aRdbPkg accordingly. Signed-off-by:
Sami Mujawar <sami.mujawar@arm.com> Reviewed-by:
Ard Biesheuvel <ardb@kernel.org>
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Sami Mujawar authored
The edk2 patch at 103fa647d159e3d76be2634d2653c2d215dd0d46 updated the ARM_CORE_INFO structure to remove the ClusterId and CoreId fields in the ARM_CORE_INFO structure in favor of a new Mpidr field. Therefore, fix the ArmPlatformLibrary instance for Platform/NXP/LS1046aFrwyPkg accordingly. Signed-off-by:
Sami Mujawar <sami.mujawar@arm.com> Reviewed-by:
Ard Biesheuvel <ardb@kernel.org>
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Sami Mujawar authored
The edk2 patch at 103fa647d159e3d76be2634d2653c2d215dd0d46 updated the ARM_CORE_INFO structure to remove the ClusterId and CoreId fields in the ARM_CORE_INFO structure in favor of a new Mpidr field. Therefore, fix the ArmPlatformLibrary instance for Platform/NXP/LS1043aRdbPkg accordingly. Signed-off-by:
Sami Mujawar <sami.mujawar@arm.com> Reviewed-by:
Ard Biesheuvel <ardb@kernel.org>
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Sami Mujawar authored
The NXP platform firmware build breaks due to the missing dependency on VariableFlashInfoLib. Therefore, to satisfy the dependency include VariableFlashInfoLib in the LibraryClasses.common section. Signed-off-by:
Sami Mujawar <sami.mujawar@arm.com> Reviewed-by:
Ard Biesheuvel <ardb@kernel.org>
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Sami Mujawar authored
The DeveloperBox platform firmware build breaks due to the missing dependency on VariableFlashInfoLib. Therefore, to satisfy the dependency include VariableFlashInfoLib in the LibraryClasses section. Signed-off-by:
Sami Mujawar <sami.mujawar@arm.com> Reviewed-by:
Ard Biesheuvel <ardb@kernel.org>
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