Mention to update submodule under for edk2-platforms. It is for RISC-V OpenSBI library.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>

Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>

1 - The SBSAQEMU_ACPI_ITOA contained a typo that put bogus characters
in the name if number of CPUs was greater than 10. It is safer to use
the AsciiSPrint function from PrintLib.

2 - The _UID fields were bogus, and indicated as bytes in AML instead of
a word. This caused extra Zeros to appear in disassembly. Fixed by
making them AML_WORD_PREFIX and putting CpuId in little endian.

3 - The table was a number of bytes too long, which causes bogus Zero in
dissassembly at end of table. Re-adjust code slightly to reduce table
size once we know the size of the length field.

Signed-off-by: Graeme Gregory <graeme@nuviainc.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>

Commit 0c2af049 added mDriverBinding
extern module global, but did not remove the STATIC declaration, which
caused the build to break. Fix the build error by removing STATIC for
that module global variable.

Signed-off-by: Samer El-Haj-Mahmoud <samer.el-haj-mahmoud@arm.com>
Reviewed-by: Pete Batard <pete@akeo.ie>
Reviewed-by: Andrei Warkentin <andrey.warkentin@gmail.com>

Signed-off-by: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>

Signed-off-by: Tanmay Jagdale <tanmay.jagdale@linaro.org>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>

Add support to create Processor Properties Topology Table at
runtime. The cache topology of each CPU is as follows:

                  CPU N
         ------------------------
         |  --------  --------  |
         |  | L1-I |  | L1-D |  |
         |  | 32KB |  | 32KB |  |
         |  --------  --------  |
         |  ------------------  |
         |  |    L2 512KB    |  |
         |  ------------------  |
         ------------------------

Signed-off-by: Tanmay Jagdale <tanmay.jagdale@linaro.org>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>

- Add support to create SSDT table at runtime. Since SSDT
  table is a data table, added a few helper macros to create
  the AML entries.
- Also added a function to calculate the length of Packages.

Signed-off-by: Tanmay Jagdale <tanmay.jagdale@linaro.org>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>

- Add support to create MADT table at runtime.
- Included a macro for GIC Redistributor structure initialisation.

Signed-off-by: Tanmay Jagdale <tanmay.jagdale@linaro.org>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>

- Add a new ACPI driver for the SbsaQemu platform which would
  handle any modifications needed for the ACPI tables.

- Add a parser function in this driver which parses the FDT created
  by Qemu to determine the number of CPUs and hence update the
  PcdCoreCount variable.

Signed-off-by: Tanmay Jagdale <tanmay.jagdale@linaro.org>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>

- Since the core count is dynamic and controlled by Qemu, move the
  PcdCoreCount from [PcdsFixedAtBuild] to [PcdsDynamic] section.

- Move FdtLib from [LibraryClasses.common.PEIM] to [LibraryClasses.common]
  section so that driver DXEs can use the device tree APIs.

Signed-off-by: Tanmay Jagdale <tanmay.jagdale@linaro.org>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>

Add PCI related entries to DSDT table along with the routing
entries. Also add the MCFG table.

Co-authored-by: Graeme Gregory <graeme.gregory@linaro.org>
Signed-off-by: Tanmay Jagdale <tanmay.jagdale@linaro.org>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>

- Add the following ACPI tables for SbsaQemu platform
    DSDT, FADT, GTDT, SPCR
- Created an Include directory to hold common header files.
- Also included the Acpiview shell utility.

Co-authored-by: Graeme Gregory <graeme.gregory@linaro.org>
Co-authored-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Signed-off-by: Tanmay Jagdale <tanmay.jagdale@linaro.org>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>

Update Maintainers.txt for RISC-V platform.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Gilbert Chen <gilbert.chen@hpe.com>
Acked-by: Leif Lindholm <leif.lindholm@linaro.org>

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
Cc: Palmer Dabbelt <palmer@sifive.com>

Update Readme.md for RISC-V platforms.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Gilbert Chen <gilbert.chen@hpe.com>
Acked-by: Leif Lindholm <leif.lindholm@linaro.org>

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
Cc: Palmer Dabbelt <palmer@sifive.com>

Initial U5SeriesPkg for U5 series platforms.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Gilbert Chen <gilbert.chen@hpe.com>
Acked-by: Leif Lindholm <leif.lindholm@linaro.org>

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
Cc: Palmer Dabbelt <palmer@sifive.com>

Initial version of SiFive U500 VC707 platform.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Reviewed-by: Gilbert Chen <gilbert.chen@hpe.com>
Acked-by: Leif Lindholm <leif.lindholm@linaro.org>

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
Cc: Palmer Dabbelt <palmer@sifive.com>

This is OpenSBI platform code implementation of U500 platform.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Reviewed-by: Gilbert Chen <gilbert.chen@hpe.com>
Acked-by: Leif Lindholm <leif.lindholm@linaro.org>

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>

PEI module for U500 platform initialization.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Reviewed-by: Gilbert Chen <gilbert.chen@hpe.com>
Acked-by: Leif Lindholm <leif.lindholm@linaro.org>

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
Cc: Palmer Dabbelt <palmer@sifive.com>

Add SiFive U540 platform build metafiles.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Reviewed-by: Gilbert Chen <gilbert.chen@hpe.com>
Acked-by: Leif Lindholm <leif.lindholm@linaro.org>

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>

This is OpenSBI platform code implementation of U540 platform.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Reviewed-by: Gilbert Chen <gilbert.chen@hpe.com>
Acked-by: Leif Lindholm <leif.lindholm@linaro.org>

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
Cc: Palmer Dabbelt <palmer@sifive.com>

Platform PEI module for U540 platform initialization.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Reviewed-by: Gilbert Chen <gilbert.chen@hpe.com>
Acked-by: Leif Lindholm <leif.lindholm@linaro.org>

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
Cc: Palmer Dabbelt <palmer@sifive.com>

Serial Port library for U5 series platform.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Gilbert Chen <gilbert.chen@hpe.com>
Acked-by: Leif Lindholm <leif.lindholm@linaro.org>

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
Cc: Palmer Dabbelt <palmer@sifive.com>

Timer library used to access to machine mode timer Control Status Registers
for U5 series platforms.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Gilbert Chen <gilbert.chen@hpe.com>
Acked-by: Leif Lindholm <leif.lindholm@linaro.org>

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
Cc: Palmer Dabbelt <palmer@sifive.com>

This will ensure that it is dispatched properly by the DXE dispatcher,
which means it doesn't have to go in the APRIORI section.

Signed-off-by: Daniel Schaefer <daniel.schaefer@hpe.com>

Cc: Abner Chang <abner.chang@hpe.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
Cc: Ard Biesheuvel <ard.biesheuvel@arm.com>

RAM based Firmware Volume Block service runtime driver for U5 series
platforms. The firmware binary image is stored in SD card and
loaded by Zero Stage Boot Loader (ZSBL) then mapped to RAM space.
This driver provides EFI Firmware Volume Block protocol to access
to firmware volume at RAM space.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Gilbert Chen <gilbert.chen@hpe.com>
Acked-by: Leif Lindholm <leif.lindholm@linaro.org>

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>

Timer DXE implementation for U5 series platform.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Reviewed-by: Gilbert Chen <gilbert.chen@hpe.com>
Acked-by: Leif Lindholm <leif.lindholm@linaro.org>

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>

This is the library to create U5MC Coreplex specific information for
U5 series platforms.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Gilbert Chen <gilbert.chen@hpe.com>
Acked-by: Leif Lindholm <leif.lindholm@linaro.org>

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
Cc: Palmer Dabbelt <palmer@sifive.com>

SiFive U54 core library for building core information hob data.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Reviewed-by: Gilbert Chen <gilbert.chen@hpe.com>
Acked-by: Leif Lindholm <leif.lindholm@linaro.org>

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
Cc: Palmer Dabbelt <palmer@sifive.com>

This is the initial version of SiFive silicon package. Provides PCD
tokens.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Gilbert Chen <gilbert.chen@hpe.com>
Acked-by: Leif Lindholm <leif.lindholm@linaro.org>

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
Cc: Palmer Dabbelt <palmer@sifive.com>

Add RISC-V platform package.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>

SecMain module for RISC-V platform.
This was cloned from OpenSBI fw_base.S
(RiscVPkg/Library/RiscVOpensbiLib/opensbi/firmware/) and revised to
edk2 framework.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>

Common Platform Boot Manager library for RISC-V platform.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>

PlatformUpdateProgressLib

NULL instance of PlatformUpdateProgressLib.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>

PlatformMemoryTestLib

NULL instance of PlatformMemoryTestLib.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>

NULL instance of RiscVOpensbiPlatformLib.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>

Add OpenSBI firmware context processor specific library which
provides interface to create processor specific firmware
context hob data.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>

RISC-V Platform Temporary Memory library

NULL instance of RISC-V Platform Temporary Memory library.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>

- Add RISC-V ProcessorPkg package which provides RISC-V processor related
  drivers and libraries.
- Support RISC-V OpenSBI and RISC-V platforms

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>

NULL instance of RISC-V platform timer library.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>

for RISC-V platforms.

RISC-V generic SMBIOS DXE driver for building up SMBIOS type 4, type 7
and type 44 records.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>