- Jan 16, 2019
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Jacob Bramley authored
Change-Id: Idaad61827b849448b177ac6ecfa9a8041e31d6af
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- Sep 26, 2018
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Jacob Bramley authored
This makes the simulation pseudo-instruction mechanism a bit more stable across VIXL versions. We still don't guarantee that simulation pseusdo-instructions generated with the MacroAssembler will work with a Simulator from a different version of VIXL, but this patch has no real cost for VIXL, and might make things easier for someone. Change-Id: Idd92328801a88f54a8d30db86304746a22ccb1df
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- Sep 24, 2018
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Jacob Bramley authored
This resovles a TODO. These instructions are already supported, but the tests were disabled. Change-Id: Ibe80f04a57e195a298acfc6b6d3d9c629a6ef3aa
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- Sep 19, 2018
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Jacob Bramley authored
This is a squashed merge of several separate patches that, combined, add support for most architectural features described up to Armv8.3. Change-Id: Ia67f25fb9b82d5968120b0b144bd232e1898dc90
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Jacob Bramley authored
Change-Id: Ib0108fe3abd65bbd3bbc94db6dc9b9c95ae86783
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- Sep 13, 2018
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Jacob Bramley authored
The Simulator supports some pseudo-instructions to configure CPU features dynamically. These are used by the test infrastructure, but only in limited use-cases. This patch adds some specialised tests to ensure that a few more corner-cases are tested. Change-Id: Ia77edfb60900362de566ffcfea4de5b6ffe634bf
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- Sep 11, 2018
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Jacob Bramley authored
This required a clean-up at the same time, to fix some inconsistencies in the way that the APIs and macros had been used. The new code structure allows for a test-runner option to print the features required by each instruction, but this is not implemented here. Change-Id: I967c8bd44f6a832892fc854ca6643a5e6a682997
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- Sep 06, 2018
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Jacob Bramley authored
This is implemented using a new decoder visitor, CPUFeaturesAuditor. This visitor holds a set of features required by the last-decoded instruction, a set of features seen since construction (or 'ResetSeenFeatures()'), and a set of features that are considered to be available. This visitor can be used by itself, but its main purpose is to implement Simulator and Disassembler support for CPUFeatures: - The Simulator creates and attaches this visitor automatically, much like it does for the disassembly trace, so existing simulation use-cases require no special user interaction. The Simulator checks that each encountered instruction only uses available features. The Simulator also supports dynamic configuration of features, in a manner similar to the trace controls. - The Disassembler does not directly interact with the CPUFeaturesAuditor, but the PrintDisassembler can be configured to annotate each instruction with required features that are missing from GetAvailableFeatures(). The PrintDisassembler is used to implement Simulator trace, so a simulation failure due to missing feature support will be immediately preceeded by a corresponding PrintDisassembler annotation (when trace is enabled). No existing test uses the PrintDisassembler in this way, so this patch also adds 'TRACE_' tests to check that the features are appropriately formatted. Change-Id: I3dc0e22f0a5bd3287ba1870539e018ff4a768a4b
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- Aug 30, 2018
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Jacob Bramley authored
Also add a few basic unit tests. Change-Id: Ibbbcaf5afe1586a5b2b1219322ddb78ad17f1218
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Jacob Bramley authored
These tests have been disabled for a long time, apparently by accident. This patch restores them, and applies fixes necessary to get them working. Notably: - Fix the simulated-runtime-calls example, and correct an ifdef to ensure that it builds. - Enable --trace-* options for test-examples, to match the behaviour of other tests. Change-Id: Iab0034f19ce935ba7237f8546f9c43f8cec13312
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Jacob Bramley authored
This allows users to use custom hints without resorting to an undefined static_cast. Also, fix disassembly of hints: - Add several named hints to the disassembler, so they can be properly disassembled. - Properly disassemble unnamed hints. Change-Id: Ia8b4d07a5bff08346faebd5b2f495d047d7037c0
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- Aug 28, 2018
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Jacob Bramley authored
FCADD and FCMLA both span multiple opcodes, so it is not easy to represent them with the Fixed/FMask/Mask structure that we usually use. In particular, the Disassembler and Simulator would handle some unallocated encodings as FCADD instructions. This patch makes disassembly precise. Change-Id: Ia0bda19489b2a1744b52a717ee7d6dc1b309184d
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Jacob Bramley authored
These features are already supported by VIXL, and they should have been enabled in the patch that introduced these tests. The noise in the diff exists because these tests are generated from a script. With this version, the generation should be made stable, so that future updates using the same script do not generate this kind of noise. Change-Id: Idd9c37e642e0c51fdba07f82a41496c9d6927c1d
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Jacob Bramley authored
These forms are allowed by the architecture, though they are functionally identical to the zero-offset forms. This patch allows index by zero for ldp and stp, and fixes the disassembly for those and the single-register loads and stores. Change-Id: I234ee88bb685b0753d20981b517ba3fc4f02dd4c
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- Aug 23, 2018
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Jacob Bramley authored
This adds a CacheOpEncoder class to encode InstructionCacheOp and DataCacheOp values, in the same way as SystemRegister. I've also replaced the hexadecimal field values with decimals, since this is easier to read and also matches the table in the Arm ARM. Change-Id: I05bb334ebce77f2b3847fb70afdfc30aaf798e30
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- Aug 16, 2018
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Jacob Bramley authored
Change-Id: Ibd10cd0b37821408fe2c5cb0c7e160938d5c8d5d
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Jacob Bramley authored
These check that the Assembler tests the correct feature sets for each instruction. Both positive and negative tests are included. These tests do not cover the MacroAssembler, but the MacroAssembler checks are almost entirely covered by the Assembler checks. Change-Id: I73c2bdf0a62def40569e5e604b447cac0f07a3dc
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Jacob Bramley authored
In particular, checking for a directory named '.git' fails when 'git-worktree' is used, since worktrees get a file named '.git', not a directory. Conveniently, Git commands in worktrees behave superficially as if the worktree is itself a normal Git repository, so we can simply ask Git for the top level directory and compare it with the provided path. Change-Id: I41ef4667ae7121b304b03f8c39ec4c700d1f1c4e
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- Aug 13, 2018
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Pierre Langlois authored
Introduce a `--clang-format PATH` option to `tools/clang_format.py` and `tools/test.py` to be able to use an clang-format other than `clang-format-3.8`. Change-Id: Iddfd963e2208cbc2a19dcc57aeea909daa28e1bc
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- Jul 20, 2018
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Jacob Bramley authored
Now, when the Assembler is asked to assemble an instruction, it asserts (in debug mode) that the necessary features are available. This also updates the tests to use no features by default, so that they must be explicitly requested in the test itself. This provides some assurance that the Assembler contains reasonable checks. This patch uses variadic macros, which are a C99/C++11 feature, and I had to silence a warning in the build system for C++98 builds. However, its use is restricted to the tests, and we already rely on some other C99 features. Change-Id: Ifb9846504f98c6d0912f60ff25f219ce2b780755
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Jacob Bramley authored
The new CPUFeatures class provides feature selection based on the ID registers in the latest (Armv8.3) Architecture Reference Manual. This patch adds the CPUFeatures class and associated tests, but does not change existing VIXL behaviour. Follow-up patches will add checks and assertions to the various VIXL components. Change-Id: I51f81b43676f7a94f406be697ca9721fd3a90fa0
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- Jul 04, 2018
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Jacob Bramley authored
The Debugger isn't well maintained, and its presence has an impact on testing and validation time. Change-Id: I9ad664ec3150e7f4ea1da2e3201682fb5684c610
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- Jun 15, 2018
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Jacob Bramley authored
Change-Id: If363f306c3052b14c3c299e6fd6f9024c4934b85
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- Jun 14, 2018
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Jacob Bramley authored
Change-Id: I7b12ee533713677bdac3f5801a95b86517c81529
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- Jun 07, 2018
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Jacob Bramley authored
Change-Id: I9c256b7fe89aae817f9e235e397aa70c104dc9dd
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- May 25, 2018
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Alexander Gilday authored
Improvements are: - Sort tests by filename so clang-format doesn't complain about include ordering. - Don't pad spaces in dummy array declarations (clang-format again) - Filter tests which require regenerating to save time Also, fix NEON 'Across' tests. Change-Id: Ifadeaea29064e16395db22ea16e9e5f63ad05819
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- May 24, 2018
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Pierre Langlois authored
C++11 deprecated the use of `throw(id)` in signatures, let's just remove it. Negative testing still works in C++98 where using `throw(id)` is allowed so it isn't useful to conditionally add it for previous versions C++. Additionally, GCC now warns by default if an exception is caught by value when its type is polymorphic (-Wcatch-value). Change-Id: I7d68c82935b4796dd0fc449228ae8df4f548574d
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Jacob Bramley authored
Change-Id: Iad57700d9e9d2ae5e3d20fbbc92ae84c2995d385
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- May 15, 2018
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Pierre Langlois authored
GCC 8 found this potential bug with its new stringop-truncation warning. https://gcc.gnu.org/onlinedocs/gcc-8.1.0/gcc/Warning-Options.html#index-Wstringop-truncation Change-Id: I49db46b35792549c5a58b3de431d02a0dd569fa1
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- May 14, 2018
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Pierre Langlois authored
This would trigger a warning in GCC 7 or higher. Change-Id: Icc3d0dace76c9fb583114bef8abcde29347bc43f
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Pierre Langlois authored
Change-Id: I1989bbd294e9d6bf67f413582a81802eeb1f4205
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- Apr 23, 2018
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Carey Williams authored
This patch adds the basic groundwork for the v8.2 half precision extension. This includes an F16 wrapper class, the fmov instruction support, tests and some related trace/logging support. The trace additions in the simulator are "disabled" as they currently cause the trace tests to fail. These need to be re-generated before we can enable their half precision support. This should be handled under a separate patch. Change-Id: I431558a21649a612ba31f91cc4ab8eba9b657947
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- Apr 19, 2018
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Alexander Gilday authored
Includes: - STLLR, STLLRB, STLLRH - LDLAR, LDLARB, LDLARH Change-Id: I6691072c4aa218eb097414a8b559623e47707078
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Alexander Gilday authored
Add support for v8.2 signed and unsigned dot product instructions: Sdot and Udot. Change-Id: I19d0ad1ad962e6c2a72efe8f62a4512e430b5e33
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- Apr 17, 2018
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Alexander Gilday authored
Part of Armv8.1 Large System Extensions. Includes: - CAS, CASA, CASL, CASAL - Compare and swap word or doubleword in memory. - CASB, CASAB, CASLB, CASALB - Compare and swap byte in memory. - CASH, CASAH, CASLH, CASALH - Compare and swap halfword in memory. - CASP, CASPA, CASPL, CASPAL - Compare and swap pair of words or doublewords in memory. Change-Id: I1b55b4f53a987c455d1cbc96210856ebeb9f63bf
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- Apr 13, 2018
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Vincent Belliard authored
Change-Id: I80e40b804cc1d4389f098de834e13ce6a042fc06
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- Apr 11, 2018
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Carey Williams authored
Rips out some more utility-like FP functions from the Simulator, so that they can be accessed by other VIXL components. This patch only covers the functions necessary to support the conversion of half precision numbers in to a decimal format, but others could follow. Modifications were also made to how we call FPProcessException() and ReadDN() from within the these functions. The latter should now be passed in as value of the new UseDefaultNaN enum and the former as an *optional* pointer to a boolean, which will be set to true if an exception is thrown. Change-Id: I2f624288ee4d201900a19fdc24278760ae027827
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- Apr 10, 2018
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Alexander Gilday authored
Change-Id: I2b490d877e7e9db77608b84ab0b92aa972a54a6d
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- Apr 04, 2018
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Pierre Langlois authored
These types are reserved for internal uses in simulators and/or disassemblers. Let's not expose them to users. Change-Id: I4e875d239b86e5a64b65f379f65c63efb4d6be9e
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- Mar 22, 2018
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Change-Id: I1d3619d7ec06f3a193f22190c6a285a87044b8bb
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