[sve] Relax the lane size restriction of register in MacroAssembler.

We decided to accept a register without lane sizes for operations in Macro
assember where it doesn't matter. For example, we don't check the lane size
for bitwise `and` vectors operation, like `__ And(z0, z1, z2)`.

We should check that if lane sizes are privided by users, they are all
the same _and_ are the valid lane sizes. For example, Since `rdffr` requires
a B-sized lane, it's invalid when passing in a lane size rather than B-sized.
Although this is essentially just a move which writes every bit to destination
register, but other lane sizes would implicitly clear bits in destination.

The calling like `__ And(z0.VnB(), z1.VnH(), z2.VnS())` is invalid because of
their lane sizes are inconsistent.

Change-Id: I7cf57fd174c9bc906f90b0710fec6739cc103448