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Commit 9a4504d0 authored by Cristian Ciocaltea's avatar Cristian Ciocaltea Committed by Steven Price
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phy: phy-rockchip-samsung-hdptx-hdmi: Add clock provider



The HDMI PHY PLL can be used as an alternative dclk source to SoC CRU.
It provides more accurate clock rates required to properly support
various display modes, e.g. those relying on non-integer refresh rates.

Also note this only works for HDMI 2.0 or bellow, e.g. cannot be used to
support HDMI 2.1 4K@120Hz mode.

Signed-off-by: default avatarCristian Ciocaltea <cristian.ciocaltea@collabora.com>
Hacked-by: Steven Price
parent a16764ed
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