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Commit d80a32fe authored by Dmitry Osipenko's avatar Dmitry Osipenko Committed by Thierry Reding
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clk: tegra: Bump SCLK clock rate to 216 MHz 



AHB DMA is a running on 1/2 of SCLK rate, APB DMA on 1/4. Increasing SCLK
rate results in an increased DMA transfer rate.

Signed-off-by: default avatarDmitry Osipenko <digetx@gmail.com>
Acked-By: default avatarPeter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 5a6b184a
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