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Commit c40d1cce authored by Nava kishore Manne's avatar Nava kishore Manne Committed by Michal Simek
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arm64: zynqmp: Label whole PL part as fpga_full region 



This will simplify dt overlay structure for the whole PL.

Signed-off-by: default avatarNava kishore Manne <nava.manne@xilinx.com>
Signed-off-by: default avatarMichal Simek <michal.simek@xilinx.com>
Signed-off-by: default avatarMichael Tretter <m.tretter@pengutronix.de>
parent 9c363392
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