EDAC: Correct impossible example cache sysfs structure

Documentation/driver-api/edac.rst gives an example for how cpu caches
should be made visible to user-space by edac drivers. These are blocks
under a device. The blocks are named things like 'L1-cache'.

It isn't possbible to do this with edac_device_alloc_ctl_info(), as
edac_device_alloc_ctl_info() initialises every block in each instance,
and uses edac_block_name as the prefix.

armada_xp_edac, highbank_l2_edac, mpc85xx_edac each have a single entry
'cpu1/L2'. octeon_edac-pc opts for a per-cpu 'cpuX/cache1' and 'cpuX/cache2'.

As cpuX/L2 is the most popular format, change the document to describe
that.

Signed-off-by: James Morse <james.morse@arm.com>