clk: meson: c3: pll: fix frac maximum value for hifi_pll

The fractional denominator of C3's hifi_pll fractional multiplier is
fixed to 100000.

Fixes: 8a9a129d ("clk: meson: c3: add support for the C3 SoC PLL clock")
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
Link: https://lore.kernel.org/r/20240909-fix_clk-v3-2-a6d8f6333c04@amlogic.com


Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>