clk: sunxi-ng: f1c100s: fix USB PHY gate bit offset

The bit offset of the USB PHY clock gate on F1C100s should be 1, not 8.

Fix this problem.

Fixes: 0380126e ("clk: sunxi-ng: add support for suniv F1C100s SoC")
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>