x86: Flush the TLB after setting user-bit

According to Intel SDM 4.10.4.3 "Optional Invalidation": "If CR4.SMEP =
0 and a paging-structure entry is modified to change the U/S flag from 0
to 1, failure to perform an invalidation may result in a "spurious"
page-fault exception (e.g., in response to an attempted user-mode
access) but no other adverse behavior."

The access test actually causes in certain environments a spurious
page-fault. So invalidate the relevant PTE after setting the user bit.

Signed-off-by: Nadav Amit <nadav.amit@gmail.com>
Message-Id: <20210617101543.180792-1-namit@vmware.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>