Readme.md to explain how to build NXP board packages.

Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

The firmware device, description and declaration files.

Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

Platform driver will be used for platform specific work.
At present, it populate i2c driver structure with platform
specific information and install RTC on i2c.

Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

Add MemoryInitPei Library for NXP platforms.
It retreieves DRAM information from TF-A.

Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>

Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

Real time clock Apis on top of I2C Apis

Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

I2C driver produces gEfiI2cMasterProtocolGuid which can be
used by other modules.

Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

Add SocInit function that initializes peripherals
and print board and soc information.

Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>

Add support to return pointer to MMIO APIs on basis of Swap flag.
If Flag is True then MMIO APIs returned in which data
swapped after reading from MMIO and before write using MMIO.

Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

This library provided MMIO APIs for modules need swapping.

Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

Leif now works at NUVIA Inc, update email address accordingly.

Cc: Andy Hayes <andy.hayes@displaylink.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Marcin Wojtas <mw@semihalf.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Pete Batard <pete@akeo.ie>
Cc: Leif Lindholm <leif@nuviainc.com>
Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>

Whether the Netsec driver is built to support coherent or non-coherent
DMA is decided by the DmaLib library class resolution that is provided
by the platform description, and there are various other places where
the platform needs to be consistent with this (ACPI tables, device
tree, platform driver, etc)

Since the driver has no way to figure out which flavor of DmaLib it was
built against, there is no point in limiting it to one flavor only, and
we can drop the DmaType check at binding time entirely.

This fixes an issue introduced by commit 88c78744
("Silicon/SynQuacer/PlatformDxe: set NETSEC DMA as coherent"), which
incorrectly stated that the driver does not look at the DmaType flag
in the first place.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

StyxSpiFvDxe depends on gEfiEventVirtualAddressChangeGuid, but got
away with not declaring it in its INF because of a transitive
dependency. However, this dependency got dropped in core EDK2,
resulting in build failures of the Styx platform.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2318



1. Add ConfigBlockLib.h and ConfigBlock.h to InstelSiliconPkg and remove all other ConfigBlockLib.h.
2. Change reference path of ConfigBlockLib to IntelSiliconPkg

Signed-off-by: Ethan Tsao <ethan.tsao@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2436



Fixed some doxygen comment that does not follow correct doxygen format.
Updated some description of some functions.

Notes:
v1:
- Initial version of code change.
v2:
- Update some description of some functions.
v3:
- Update some description of some functions.
v4:
- Change "post" to "POST".
v5:
- Fixed typo of subject from "Doxcgen" to "Doxygen".

Cc: Michael Kubacki <michael.a.kubacki@intel.com>
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Shenglei Zhang <shenglei.zhang@intel.com>
Signed-off-by: Marc Chen <marc.w.chen@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Sai Chaganty <rangasai.v.chaganty@intel.com>

The function has NO comment immediately preceding it.
Need to remove the space between the function and the comment

Signed-off-by: Evelyn Wang <iwen.evelyn.wang@intel.com>
Cc: Jenny Huang <jenny.huang@intel.com>
Cc: More Shih <more.shih@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Sai Chaganty <rangasai.v.chaganty@intel.com>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>

The PCD PcdArmReenterPeiForCapsuleWarmReboot is going away so drop the
definition for DeveloperBox.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

This reverts commit dad93819 which caused Whiskeylake/Kabylake
OpenBoardPkg fail to build.

Signed-off-by: Ray Ni <ray.ni@intel.com>

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2318



Move ConfigBlockLib.h and ConfigBlock.h to InstelSiliconPkg and remove all other ConfigBlockLib.h and ConfigBlock.h

Signed-off-by: Ethan Tsao <ethan.tsao@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>

Since official TCG definition is added to MdePkg, IntelPciDeviceSecurityDxe
should not define its own TCG event log.

Cc: Ray Ni <ray.ni@intel.com>
Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>

8b72f720 introduced a regression bug that make GenBiosId
failed if -ot is passed to this tool.

This patch is going to fix it.

Signed-off-by: Bob Feng <bob.c.feng@intel.com>

Cc: Liming Gao <liming.gao@intel.com>
Cc: Kilian Kegel <kilian_kegel@outlook.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>

Adds a dynamic PCD that specifies whether the feature is active.

This is useful because the feature might be enabled via FeatureFlag
PCD PcdAcpiDebugFeatureEnable meaning it is built and included in
the flash image but the board might need to control whether the
feature is active based on input such as a Setup menu option.

A deactivated feature will be dispatched but simply exit in the
entry point.

Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Signed-off-by: Michael Kubacki <michael.a.kubacki@intel.com>
Reviewed-by: Sai Chaganty <rangasai.v.chaganty@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>

This is an improvement of e9db0463
where we inhibit serial output of MMIO mapped UARTs to all runtime
drivers rather than just RTC, as other drivers may crash the OS
just the same.

Also add it to the Pi 4 platform where it was missing altogether.

Signed-off-by: Pete Batard <pete@akeo.ie>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

Add an ACPI_BASIC_MODE_ENABLE flag to produces builds intended to run in
ACPI mode without any additional requirements (memory limits, acpi=force,
etc).

This flag is disabled by default.

Signed-off-by: Pete Batard <pete@akeo.ie>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

Since the RPi4 PCIe host bridge is not ECAM compliant, we can
not expose it as a host bridge to the OS via ACPI. However,
given the hardwired nature of this platform, we can expose the
xHCI controller that is guaranteed to live at the base of the
MMIO32 BAR window as a platform device directly.

It should be noted that the xHCI table is not finalized at this
stage, as Windows xHCI support is still a major question mark.

Signed-off-by: Pete Batard <pete@akeo.ie>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

The PL011 can be a better choice for the serial console on the RPi4,
given that its baud clock is not derived from the CPU clock (which
may change under our feet unless we keep it fixed at a low rate), and
given the fact that the SBSA/SBBR specs that describe ARM specific
architectural requirements for ACPI only permit PL011 based UARTs to
begin with.

Therefore we add a new PL011_ENABLE build switch to tell the firmware
to use PL011 for all console serial I/O, including for TF-A, SPCR and
DBG2, as well as toggle the BlueTooth module to use the mini UART.

For the time being, the option is disabled by default because it
requires an overlay to be enabled in config.txt that pinmuxes the
PL011 TX/RX lines to the UART pins on the connector block.

Signed-off-by: Pete Batard <pete@akeo.ie>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

Use code derived from JunoPkg to generate our serial tables and
also use PCDs where possible.

Signed-off-by: Pete Batard <pete@akeo.ie>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

Use a proper aslc source to build the table.

Note that we use ACPI 5.1 for this table to match the MADT
constraints.

Signed-off-by: Pete Batard <pete@akeo.ie>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

* Use ACPI 5.1 everywhere, since we are constrained to use v5.x for
  MADT compatibility.
* Clean up whitespaces and reorganize header declaration.
* Prefix all RPi related constant with RPI_ to make them clearer to
  differentiate from regular EDK2 ones.
* Reference IndustryStandard/Acpi.h always.
* Remove explicit references to RPI4 for sources that we may be
  factorized for both the Pi 3 and Pi 4 platform.

Signed-off-by: Pete Batard <pete@akeo.ie>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

This adds offset, base address, interrupt and register-space length
for the 2 UARTs that the Bcm283x SoC provides.

To be consistent, we simplify the two other existing base address
definitions to a more legible equivalent since there is no point
in explicit refs to FixedPcdGet64 (PcdBcm283xRegistersAddress).

Signed-off-by: Pete Batard <pete@akeo.ie>
Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2409



Updated WhiskeylakeURvp PCDs to enable FSP/BL stack sharing.

This fixes the boot failure seen with the latest Coffee Lake (CFL)
FSP binary (v 7.0.68.41).

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Michael Kubacki <michael.a.kubacki@intel.com>
Co-authored-by: Michael Kubacki <michael.a.kubacki@intel.com>
Signed-off-by: Prince Agyeman <prince.agyeman@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>

This uses the recently introduced NonCoherentIoMmuDxe for PCIe access
and should enable USB device usage in the UEFI environment.

As mentioned in https://lkml.org/lkml/2019/9/9/170

, imposing a 3 GB
DMA limit might be necessary for the 4 GB models so we follow suit by
setting PcdDmaDeviceLimit to 3 GB - 1 in NonCoherentIoMmuDxe.

Note that this patch does not provide xHCI ACPI support because the
required Xhci.asl table will be provided in a later commit.

Signed-off-by: Pete Batard <pete@akeo.ie>
Acked-by: Philippe Mathieu-Daude <philmd@redhat.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

Enables the instantiation of the PCI host bridge.

Signed-off-by: Pete Batard <pete@akeo.ie>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

This SoC uses a nonstantard ECAM with requires the provision of a custom
segment library. Basically, with the Bcm2711, the root port is the first
bytes of the register space (offset 0) and individual devices are selected
by computing their BDF index and writing that into the CFG_INDEX register
before ECAM data can then be read/written at CFG_DATA.

We also ensure that read/write accesses are serialized through the use of
a lock, as some of the library calls cannot run concurrently.

Signed-off-by: Pete Batard <pete@akeo.ie>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

This populates all of the define's we need for PCIe accesses.
Four new PCDs are also introduced for the register and MMIO platform
constants.

Signed-off-by: Pete Batard <pete@akeo.ie>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2330



Changes:
* Added CmosMap.h that defines CMOS addresses used in
  SimicsOpenBoardPkg as macros

* Replaced hardcoded CMOS addresses with the macros
  defined in CmosMap.h

Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Michael Kubacki <michael.a.kubacki@intel.com>
Signed-off-by: Prince Agyeman <prince.agyeman@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
Reviewed-by: Michael Kubacki <michael.a.kubacki@intel.com>

This enables building the initial RPi4 platform firmware.

Note that PCIe and xHCI are missing at this stage and that this
version of the firmware uses miniUART for serial I/O. PCIe and
xHCI support will be added in a later patch series as well as
the ability to switch between PL011 and miniUART for serial.

Details on how to use the resulting firmware, and especially how
to configure the media for boot, are provided in the Readme.

Signed-off-by: Pete Batard <pete@akeo.ie>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

Update CSRT, DSDT, GTDT, MADT, SDHC and serial tables for the new
base addresses and switch ACPI to GIC.

We use ACPI 5.1 for MADT because older versions of the Linux kernel
can be finicky when it comes to checking the size of the GICC entries
the table: depending on the FADT version (either 5, or 6 or later),
the size must be exactly 76 or 80 bytes, respectively. However, using
the ACPI 6.0 or 6.1 GICC macros results in 80 byte entries, which
triggers a mismatch error since the FADT we are exposing is 5.1.

Since GICv2 doesn't care about any of the fields that were added
after ACPI 5.1, we can simply use that version to keep Linux happy.

Signed-off-by: Pete Batard <pete@akeo.ie>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

For this initial commit, we duplicate the RPi3 ones.

Signed-off-by: Pete Batard <pete@akeo.ie>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>