Add Readme for LoogArch and Modify the Readme in the root directory.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4054



Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Bibo Mao <maobibo@loongson.cn>
Cc: Chao Li <lichao@loongson.cn>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: xianglai li <lixianglai@loongson.cn>
Reviewed-by: Chao Li <lichao@loongson.cn>

Support Dxe for LoogArch.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4054



Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Bibo Mao <maobibo@loongson.cn>
Cc: Chao Li <lichao@loongson.cn>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: xianglai li <lixianglai@loongson.cn>
Reviewed-by: Chao Li <lichao@loongson.cn>

This library provides interfaces related to Dxe Hob.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4054



Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Bibo Mao <maobibo@loongson.cn>
Cc: Chao Li <lichao@loongson.cn>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: xianglai li <lixianglai@loongson.cn>
Reviewed-by: Chao Li <lichao@loongson.cn>

This library provides interfaces related to restart and shutdown.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4054



Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Bibo Mao <maobibo@loongson.cn>
Cc: Chao Li <lichao@loongson.cn>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: xianglai li <lixianglai@loongson.cn>
Reviewed-by: Chao Li <lichao@loongson.cn>

The Library provides Boot Manager interfaces.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4054



Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Bibo Mao <maobibo@loongson.cn>
Cc: Chao Li <lichao@loongson.cn>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: xianglai li <lixianglai@loongson.cn>
Reviewed-by: Chao Li <lichao@loongson.cn>

This library provides interfaces such as
real-time clock initialization
to get time and setting time.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4054



Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Bibo Mao <maobibo@loongson.cn>
Cc: Chao Li <lichao@loongson.cn>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: xianglai li <lixianglai@loongson.cn>
Reviewed-by: Chao Li <lichao@loongson.cn>

This driver produces Timer Architectural Protocol,
Registers a timer interrupt and initializes the timer.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4054



Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Bibo Mao <maobibo@loongson.cn>
Cc: Chao Li <lichao@loongson.cn>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: xianglai li <lixianglai@loongson.cn>
Reviewed-by: Chao Li <lichao@loongson.cn>

Add PCI CpuIo protocol.there is no fix translation
offset between I/O port accesses and MMIO accesses.
Add PciCpuIo2Dxe driver to implement EFI_CPU_IO2_PROTOCOL
to add the translation for IO access.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4054



Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Bibo Mao <maobibo@loongson.cn>
Cc: Chao Li <lichao@loongson.cn>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: xianglai li <lixianglai@loongson.cn>
Reviewed-by: Chao Li <lichao@loongson.cn>

The driver produces EFI_CPU_ARCH_PROTOCOL,
Initialize the exception entry address.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4054



Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Bibo Mao <maobibo@loongson.cn>
Cc: Chao Li <lichao@loongson.cn>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: xianglai li <lixianglai@loongson.cn>
Reviewed-by: Chao Li <lichao@loongson.cn>

Platform PEI module for LoongArch platform initialization.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4054



Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Bibo Mao <maobibo@loongson.cn>
Cc: Chao Li <lichao@loongson.cn>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: xianglai li <lixianglai@loongson.cn>
Reviewed-by: Chao Li <lichao@loongson.cn>

This library provides a delay interface and a timing interface.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4054



Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Bibo Mao <maobibo@loongson.cn>
Cc: Chao Li <lichao@loongson.cn>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: xianglai li <lixianglai@loongson.cn>
Reviewed-by: Chao Li <lichao@loongson.cn>

Read the memory map information through the QemuFwCfg interface,
then build the page table through the memory map information,
and finally enable Mmu.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4054



Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Bibo Mao <maobibo@loongson.cn>
Cc: Chao Li <lichao@loongson.cn>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: xianglai li <lixianglai@loongson.cn>
Reviewed-by: Chao Li <lichao@loongson.cn>

QemuFwCfgLib for PEI phase.
This library obtains the QemuFWCfg base address by
directly parsing the fdt, and reads and writes the data
in the QemuFWCfg by operating on the QemuFWCfg base address.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4054



Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Bibo Mao <maobibo@loongson.cn>
Cc: Chao Li <lichao@loongson.cn>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: xianglai li <lixianglai@loongson.cn>
Reviewed-by: Chao Li <lichao@loongson.cn>

Use a register to save PeiServicesTable pointer,
This lib Provides PeiServicesTable pointer saving
and retrieval services.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4054



Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Bibo Mao <maobibo@loongson.cn>
Cc: Chao Li <lichao@loongson.cn>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: xianglai li <lixianglai@loongson.cn>
Reviewed-by: Chao Li <lichao@loongson.cn>

Add SEC Code And Readme.md for LoongArchQemu

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4054



Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Bibo Mao <maobibo@loongson.cn>
Cc: Chao Li <lichao@loongson.cn>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: xianglai li <lixianglai@loongson.cn>
Reviewed-by: Chao Li <lichao@loongson.cn>

Serial Port library for LoongarchQemuPkg

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4054



Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Bibo Mao <maobibo@loongson.cn>
Cc: Chao Li <lichao@loongson.cn>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: xianglai li <lixianglai@loongson.cn>
Reviewed-by: Chao Li <lichao@loongson.cn>

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4159



VmgExitLib is renamed as CcExitLib in EDK2. This change should be
applied in WhitleyOpenBoardPkg as well.

Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Signed-off-by: Min Xu <min.m.xu@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4159



VmgExitLib is renamed as CcExitLib in EDK2. This change should be
applied in Vlv2TbltDevicePkg as well.

Cc: Zailiang Sun <zailiang.sun@intel.com>
Cc: Yi Qian <yi.qian@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Signed-off-by: Min Xu <min.m.xu@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4159



VmgExitLib is renamed as CcExitLib in EDK2. This change should be
applied in SimcOpenBoardPlatformPkg as well.

Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Signed-off-by: Min Xu <min.m.xu@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4159



VmgExitLib is renamed as CcExitLib in EDK2. This change should be
applied in QuarkPlatformPkg as well.

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Kelly Steele <kelly.steele@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Signed-off-by: Min Xu <min.m.xu@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4159



VmgExitLib is renamed as CcExitLib in EDK2. This change should be
applied in MinPlatformPkg as well.

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Signed-off-by: Min Xu <min.m.xu@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4155



With new implementation, FITGEN will populate info needed
for the PROT assisted BootGuard solution and TXT on servers
using FIT 4 Entry. FitGen based on the CPU FMS FITGEN will
decide to call one of the two Type 2 FIT entry.

Signed-off-by: Rahul R Kumar <rahul.r.kumar@intel.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>

CreateSecondLevelPagingEntryTable() has a return type of
VTD_SECOND_LEVEL_PAGING_ENTRY * and an error condition
returns a value of NULL.

Change return value of EFI_SUCCESS (value 0) to NULL to
address CLANG compiler detection of incorrect return type.

Cc: Ray Ni <ray.ni@intel.com>
Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Ashraf Ali S <ashraf.ali.s@intel.com>
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>

CreateSecondLevelPagingEntryTable() has a return type of
VTD_SECOND_LEVEL_PAGING_ENTRY * and an error condition
returns a value of NULL.

Change return value of EFI_SUCCESS (value 0) to NULL to
address CLANG compiler detection of incorrect return type.

Cc: Ray Ni <ray.ni@intel.com>
Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Ashraf Ali S <ashraf.ali.s@intel.com>
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Sai Chaganty <rangasai.v.chaganty@intel.com>

Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Graeme Gregory <graeme@nuviainc.com>
Cc: Graeme Gregory <quic_ggregory@quicinc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Acked-by: Graeme Gregory <quic_ggregory@quicinc.com>

Pierre Gondois authored Sep 08, 2022 and Sami Mujawar committed Nov 01, 2022

From ACPI 5.1, s19.5.28 DefinitionBlock (Declare Definition Block):
  Note: For compatibility with ACPI versions before
  ACPI 2.0, the bit width of Integer objects is
  dependent on the ComplianceRevision of the DSDT.
  If the ComplianceRevision is less than 2, all
  integers are restricted to 32 bits. Otherwise,
  full 64-bit integers are used. The version of the DSDT
  sets the global integer width for all integers,
  including integers in SSDTs.

To be up-to-date with the latest table revision, bump the version
of all dsdt/ssdt tables that are relying on an ACPI specification
version above 2.0.

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4086



This commit adds support for new FIT record type for
Vendor Authorized Boot (VAB) security technology(FIT spec revision 1.4).
VAB defines 3 new following types
Vendor Authorized Boot Provisioning Table (Type 0x1A)
Vendor Authorized Boot Image Manifest (Type 0x1B)
Vendor Authorized Boot Key Manifest (Type 0x1C)
The code has been updated to align these binaries on 64 byte boundary
and not to overlap with other regions, similar to Key manifest,
Boot Policy manifest and other optional types.

Also added macros to define FIT spec Major and Minor version numbers and
print the same instead of hardcoded string.

Signed-off-by: Pavamana Holavanahalli <pavamana.hv@intel.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>

Commit 005ab4a1
("Maintainers.txt: Update reviewers for IntelSiliconPkg")
introduced incorrect line ending on the added line. Tidy this up.

Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>

Switch to the OVMF version of the NOR flash DXE driver, which supports
QEMU's NOR flash emulation specifically, and carries some optimizations
that are therefore permitted.

Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4095



Updates several debug macros in TigerlakeSiliconPkg to correctly
match print specifiers to actual arguments.

Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Heng Luo <heng.luo@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4095



Updates several debug macros in KabylakeSiliconPkg to correctly
match print specifiers to actual arguments.

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4095



Updates several debug macros in CoffeelakeSiliconPkg to correctly
match print specifiers to actual arguments.

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>

Drop the dependency on the ArmPlatformPkg version of NorFlashDxe and
NorFlashStandaloneMm, which will be going away soon. Instead, depend on
the local version under Platform/ARM.

Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>

The ArmPlatformPkg version of NorFlashDxe and NorFlashStandaloneMm will
be going away, so clone them into Platform/ARM where the ARM platforms
that rely on this driver can keep using it.

Other than updating the INF version, refreshing the file GUIDs and
reorganizing the various INF sections, no changes have been made to the
driver.

Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>

The version of NorFlashPlatformLib defined in ArmPlatformPkg will go
away once we retire its version of NorFlashDxe, so switch to a local
Platform/ARM version instead.

Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>

Don't include NorFlashPlatformLib.h unnecessarily from BootMonFs, and
drop the reference to ArmPlatformPkg.dec, which isn't needed after that
either.

Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>

Fip006Dxe is part of the SynQuacer platform, which is its only user, and
yet, it relies on NorFlashPlatformLib to carry the platform specific NOR
geometry. This library is tied to ArmPlatformPkg's NorFlashDxe, which
will be going away, so let's stop using it.

Since the abstraction serves no purpose here, let's just merge the
library with its only user.

Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>

The Comcast RDK platform was contributed years ago, but since then,
nobody has expressed any interest in it, leaving it to the maintainers
to keep it in shape. As it turns out, the maintainers can think of
better ways to spend their time, so let's just drop it.

Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>

Refine the DRHD table print message.
Remove unused variable.

Hsd-es-id: 15012152545
Signed-off-by: Sheng Wei <w.sheng@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
Cc: Jenny Huang <jenny.huang@intel.com>
Reviewed-by: Robert Kowalewski <robert.kowalewski@intel.com>

Use silicon code to detect S3 resume state. Apply some relevant policy
modifications.

PcdPeiMemSize must be in common scope, for a DXE module to allocate
required memory. Libraries that produce required PPIs are defined.

BootScriptExecutorDxe should only be linked against a functionally
compatible debug stack.

Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Ankit Sinha <ankit.sinha@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Jeremy Soller <jeremy@system76.com>
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-by: Isaac Oram <isaac.w.oram@intel.com>