Rebecca Cran authored May 28, 2021 and Sami Mujawar committed Jun 07, 2021

Arm now provides the latest gcc toolchains for aarch64 and arm: the
Linaro page that was linked to no longer exists.

Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>

Rebecca Cran authored May 28, 2021 and Sami Mujawar committed Jun 07, 2021

The repo with the Visual Studio support no longer exists.
fiptool from the prebuilt_tools repo doesn't work due to a missing
dependency on libcrypto.so.1.0.0, so tell users to build it from the
trusted-firmware-a repo instead.
There's a newer version of fvp-uefi.zip that was released in 2020.

Signed-off-by: Rebecca Cran <rebecca@bsdio.com>
Reviewed-by: Chris Jones <christopher.jones@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>

Currently script Python interpreter is inconsistent with the
interpreter specified by Python home. This patch is to change
pythonhome to sys.executable.

Signed-off-by: MingYue Liang <mingyuex.liang@intel.com>
Cc: Yuwei Chen <yuwei.chen@intel.com>
Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>

Sayanta Pattanayak authored May 24, 2021 and Sami Mujawar committed Jun 02, 2021

Enable the use of UEFI secure boot for Arm's Neoverse reference design
platforms. The UEFI authenticated variable store uses NOR flash 2 which
is accessible from Standalone MM context residing in a secure partition.

Signed-off-by: Sayanta Pattanayak <sayanta.pattanayak@arm.com>
Reviewed-by: Thomas Abraham <thomas.abraham@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>

Sayanta Pattanayak authored May 24, 2021 and Sami Mujawar committed Jun 02, 2021

Add the NorFlashPlatformLib library instance that can be linked with
MM_STANDALONE modules that implement a secure variable storage. The
third instance of the NOR flash is used as the non-volatile storage.

Signed-off-by: Sayanta Pattanayak <sayanta.pattanayak@arm.com>
Reviewed-by: Thomas Abraham <thomas.abraham@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>

Sayanta Pattanayak authored May 24, 2021 and Sami Mujawar committed Jun 02, 2021

The RD-N2 platform has a different memory map from that of the other
platforms supported under the SgiPkg. To enable the use of StandaloneMM
as a secure partition on RD-N2 platform, refactor the existing
StandaloneMM platform description file. The differing portions are split
into two different files and the rest of the  platform description file
is converted into a include file.

Signed-off-by: Sayanta Pattanayak <sayanta.pattanayak@arm.com>
Reviewed-by: Thomas Abraham <thomas.abraham@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>

Add queued invalidation interface support for VTd core driver.
For software to invalidate the various caching structures, the architecture
 supports the following two types of invalidation interfaces.
1. Register-based invalidation interface
2. Queued invalidation interface.
BIOS shall check VER_REG to determine if register based invalidation can
 be used. Only for Major Version 6 or lower can support register based
 invalidation. For any version newer than that should use queue
 invalidation interface instead.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3366



Signed-off-by: Sheng Wei <w.sheng@intel.com>
Cc: Jenny Huang <jenny.huang@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
Reviewed-by: Jenny Huang <jenny.huang@intel.com>

Apply multiple fixes to the Marvell RealTimeClockLib wakeup
library callbacks.

LibGetWakeupTime:
* Add input parameters validation
* Fix 'Pending' value check

LibSetWakeupTime:
* Allow disabling the wakeup timer regardless the input 'Time' value
* Use more generic 'Time' value verification, which is more strict
  than the replaced custom one.
* Use proper alarm mask for 'Pending' signalling

With above the ACS3.0 FWTS and SCT timer tests pass cleanly.

Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>

The Marvell implementation of the RealTimeClockLib was unnecessarily
overriding the daylight and timezone values, which are handled
by non-volatile variables in the generic code. Fix that.

Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Samer El-Haj-Mahmoud <Samer.El-Haj-Mahmoud@arm.com>

The CN9131 variant's SSDT comprised UID's, whose values
overlapped the ones used in the main DSDT file. Fix that.

Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-By: Samer El-Haj-Mahmoud <Samer.El-Haj-Mahmoud@arm.com>
Reviewed-by: Sunny Wang <sunny.wang@arm.com>

DBG2 ACPI table description [1] specifies three subtypes
related to 16550 UART:
0x0 - 16550 compatible
0x1 - 16550 subset
0x12 - 16550 compatible with parameters defined in
       Generic Address Structure (GAS)

It turned out however, that the Windows OS treats 0x0 subtype as
legacy x86 UART with 8-bit access. ARM SoCs can use types 0x1 (16550 with
fixed mmio32 access) or 0x12 (16550 with fully respected GAS contents).

Switch Marvell SoCs ACPI UART subtype to 0x1 - thanks to that the
same firmware can run properly with UART output in Windows 10, Linux
and ESXI hypervisor.

[1] https://docs.microsoft.com/en-us/windows-hardware/drivers/bringup/acpi-debug-port-table



Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-By: Samer El-Haj-Mahmoud <Samer.El-Haj-Mahmoud@arm.com>
Reviewed-by: Sunny Wang <sunny.wang@arm.com>

Resolution of the DebugLib for the DXE_RUNTIME_DRIVER library
class was limited to non-RELEASE builds. This caused crashes
during FWTS in case the RT attempted to use UART. Fix that
by allowing to use DxeRuntimeDebugLibSerialPort in all kind
of builds.

Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-By: Samer El-Haj-Mahmoud <Samer.El-Haj-Mahmoud@arm.com>
Reviewed-by: Sunny Wang <sunny.wang@arm.com>

This patch adds missing entries required for SMBIOS v3.2 compliance
of the Type17 table. On the occasion improve Type4 table contents.

Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Samer El-Haj-Mahmoud <Samer.El-Haj-Mahmoud@arm.com>

Pranav Madhu authored May 25, 2021 and Sami Mujawar committed Jun 01, 2021

Extend the SMBIOS support for RD-N2-Cfg1 platform. RD-N2-Cfg1 platform
is a derivative of the RD-N2 platform and so most of the table values
for RD-N2 platform is reused.

Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
Reviewed-by: Thomas Abraham <thomas.abraham@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>

Pranav Madhu authored May 25, 2021 and Sami Mujawar committed Jun 01, 2021

Add the RD-N2-Cfg1 platform identification values including the part
number and configuration number. This information will be used in
populating the SMBIOS tables.

Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
Reviewed-by: Thomas Abraham <thomas.abraham@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>

Pranav Madhu authored May 25, 2021 and Sami Mujawar committed Jun 01, 2021

Enable ACPI CPPC mechanism for RD-N2-Cfg1 as defined by the ACPI
specification. The implementation uses AMU registers accessible as
Fixed-feature Hardware (FFixedHW) for monitoring the performance.
Non-secure SCMI fastchannels are used to communicate with SCP to set
the desired performance. RD-N2-Cfg1 platform does not support CPPC
revision 1 and below. So update the _OSC method to let OSPM know about
this fact.

Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
Reviewed-by: Thomas Abraham <thomas.abraham@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>

Pranav Madhu authored May 25, 2021 and Sami Mujawar committed Jun 01, 2021

RD-N2-Cfg1 platform supports 2 LPI states, LPI1 (Standby WFI) and LPI3
(Power-down) and the cluster supports LPI2 (Power-down) state. The LPI
implementation also supports combined power state for core and cluster.

Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
Reviewed-by: Thomas Abraham <thomas.abraham@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>

Pranav Madhu authored May 25, 2021 and Sami Mujawar committed Jun 01, 2021

The RD-N2-Cfg1 platform includes eight single-thread CPUS. Each of the
CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache and 1MB L2
cache. The platform also includes a system level cache of 8MB. Add PPTT
table for RD-N2-Cfg1 platform with this information.

Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
Reviewed-by: Thomas Abraham <thomas.abraham@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>

Aditya Angadi authored May 25, 2021 and Sami Mujawar committed Jun 01, 2021

Arm's RD-N2-Cfg1 platform is a variant of the RD-N2 platform. Compared
to RD-N2 platform, RD-N2-Cfg1 has a reduced core count of eight Neoverse
N2 CPUs and a smaller interconnect mesh. As part of the initial platform
support for RD-N2-Cfg1 platform, add the corresponding ACPI tables,
platform and flash description files.

Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
Reviewed-by: Thomas Abraham <thomas.abraham@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>

Pranav Madhu authored May 24, 2021 and Sami Mujawar committed Jun 01, 2021

Add the SMBIOS type 32 table (System Boot Information) that includes
information about the System Boot Status.

Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
Reviewed-by: Thomas Abraham <thomas.abraham@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>

Pranav Madhu authored May 24, 2021 and Sami Mujawar committed Jun 01, 2021

Add the SMBIOS type 19 table (Memory Array Mapped Addr) that includes
information about the address mapping for a Physical Memory Array.

Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
Reviewed-by: Thomas Abraham <thomas.abraham@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>

Pranav Madhu authored May 24, 2021 and Sami Mujawar committed Jun 01, 2021

Add the SMBIOS type 17 table (Memory Device) that includes the
specification of each installed memory device such as size of each
device, bank locator, memory device type, and other related information.

Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
Reviewed-by: Thomas Abraham <thomas.abraham@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>

Pranav Madhu authored May 24, 2021 and Sami Mujawar committed Jun 01, 2021

Add the SMBIOS type 16 table (Physical Memory Array) describes a
collection of memory devices that operate together to form a memory
address. It includes information about number of devices, total memory
installed, error correction mechanism used and other related information.

Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
Reviewed-by: Thomas Abraham <thomas.abraham@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>

Pranav Madhu authored May 24, 2021 and Sami Mujawar committed Jun 01, 2021

Add the SMBIOS type 7 table (Cache Information) that includes
information about cache levels implemented, cache configuration, ways of
associativity and other information related to cache memory installed.

Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
Reviewed-by: Thomas Abraham <thomas.abraham@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>

Pranav Madhu authored May 24, 2021 and Sami Mujawar committed Jun 01, 2021

Add the SMBIOS type 4 table (Processor Information) that includes
information about manufacture, family, processor id, maximum operating
frequency, and other information related to the processor.

Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
Reviewed-by: Thomas Abraham <thomas.abraham@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>

Pranav Madhu authored May 24, 2021 and Sami Mujawar committed Jun 01, 2021

Add the SMBIOS type 3 table (System Enclosure) that includes information
about manufacturer, type, serial number and other information related to
system enclosure.

Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
Reviewed-by: Thomas Abraham <thomas.abraham@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>

Pranav Madhu authored May 24, 2021 and Sami Mujawar committed Jun 01, 2021

Add the SMBIOS type 1 table (System Information) that includes
information about manufacturer, product name, version, serial number and
other information related to the system identification.

Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
Reviewed-by: Thomas Abraham <thomas.abraham@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>

Pranav Madhu authored May 24, 2021 and Sami Mujawar committed Jun 01, 2021

SMBIOS provides basic hardware and firmware configuration information
through table-driven data structure. This patch adds SMBIOS driver
support that allows for installation of multiple SMBIOS types. Also add
SMBIOS Type0 (BIOS Information) table, that include information about
BIOS vendor name, version, SMBIOS version and other information related
to BIOS.

Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
Reviewed-by: Thomas Abraham <thomas.abraham@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>

Pranav Madhu authored May 24, 2021 and Sami Mujawar committed Jun 01, 2021

Add GetProductId API for SGI/RD Platform. The API returns a product id
in integer format based on the platform description data. The product id
is required for other drivers such as SMBIOS.

Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
Reviewed-by: Thomas Abraham <thomas.abraham@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>

Pranav Madhu authored May 24, 2021 and Sami Mujawar committed Jun 01, 2021

Add RD-N2 platform identification values including the part number
and configuration number. This information will be used in populating
the SMBIOS tables.

Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
Reviewed-by: Thomas Abraham <thomas.abraham@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3412



Python38 installation path have three options.
(a) C:\Users\<UserName>\AppData\Local\Program\Python\Python38
(b) C:\Python38
(c) C:\Program Files\Python38

Issue only happens on (a) and (c).
(a) happen on <UserName> have whitespace. Ex: Tony Chen
(c) happen on "Program Files" have whitespace.

Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Signed-off-by: IanX Kuo <ianx.kuo@intel.com>

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3404



Commit d3c10d32 introduced a build error in ReportCpuHobLib.c:

IntelSiliconPkg\Library\ReportCpuHobLib\ReportCpuHobLib.c(30):
  error C2220: warning treated as error - no 'object' file generated
IntelSiliconPkg\Library\ReportCpuHobLib\ReportCpuHobLib.c(30):
  warning C4244: '=': conversion from 'UINT32' to 'UINT8',
  possible loss of data

This commit explicitly cast the assignment to fix the build error.

Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
Cc: SofiaX Chuang <sofiax.chuang@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3298



Move ReportCpuHob library from MinPlatformPkg to IntelSiliconPkg.

Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
Reviewed-by: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
Reviewed-by: Deepika Kethi Reddy <deepika.kethi.reddy@intel.com>
Reviewed-by: Kathappan Esakkithevar <kathappan.esakkithevar@intel.com>

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3298



Move ReportCpuHob library from MinPlatformPkg to IntelSiliconPkg.

Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Eric Dong <eric.dong@intel.com>

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3298



Move ReportCpuHob library from MinPlatformPkg to IntelSiliconPkg.

Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3298



Move ReportCpuHob library from MinPlatformPkg to IntelSiliconPkg.

Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
Reviewed-by: Jeremy Soller <jeremy@system76.com>

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3298



Move ReportCpuHob library from MinPlatformPkg to IntelSiliconPkg.

Reviewed-by: Agyeman Prince <prince.agyeman@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3298



Move ReportCpuHob library from MinPlatformPkg to IntelSiliconPkg.

Reviewed-by: Sai Chaganty <rangasai.v.chaganty@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
Reviewed-by: Heng Luo <heng.luo@intel.com>

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3298



Add ReportCpuHobLib

Signed-off-by: SofiaX Chuang <sofiax.chuang@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3334



There are following PCDs in IntelFsp2WrapperPkg for microcode location:

* IntelFsp2WrapperPkg:
  PcdCpuMicrocodePatchAddress
  PcdCpuMicrocodePatchRegionSize
  PcdFlashMicrocodeOffset

The change simplify the platform code to use following PCDs instead:
* MinPlatformPkg
  PcdFlashFvMicrocodeOffset
  PcdFlashFvMicrocodeBase = $(BIOS_BASE) + PcdFlashFvMicrocodeOffset
  PcdFlashFvMicrocodeSize
  PcdMicrocodeOffsetInFv <NEW>

Signed-off-by: Jason Lou <yun.lou@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>