Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Mike Kinney <michael.d.kinney@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Mohamed Abbas <mohamed.abbas@intel.com>
Cc: Michael Kubacki <michael.kubacki@microsoft.com>
Cc: Zachary Bobroff <zacharyb@ami.com>
Cc: Harikrishna Doppalapudi <harikrishnad@ami.com>
Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
Reviewed-by: Isaac Oram <isaac.w.oram@intel.com>

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Mike Kinney <michael.d.kinney@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Mohamed Abbas <mohamed.abbas@intel.com>
Cc: Michael Kubacki <michael.kubacki@microsoft.com>
Cc: Zachary Bobroff <zacharyb@ami.com>
Cc: Harikrishna Doppalapudi <harikrishnad@ami.com>
Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
Reviewed-by: Isaac Oram <isaac.w.oram@intel.com>

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Mike Kinney <michael.d.kinney@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Mohamed Abbas <mohamed.abbas@intel.com>
Cc: Michael Kubacki <michael.kubacki@microsoft.com>
Cc: Zachary Bobroff <zacharyb@ami.com>
Cc: Harikrishna Doppalapudi <harikrishnad@ami.com>
Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
Reviewed-by: Isaac Oram <isaac.w.oram@intel.com>

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Mike Kinney <michael.d.kinney@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Mohamed Abbas <mohamed.abbas@intel.com>
Cc: Michael Kubacki <michael.kubacki@microsoft.com>
Cc: Zachary Bobroff <zacharyb@ami.com>
Cc: Harikrishna Doppalapudi <harikrishnad@ami.com>
Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
Reviewed-by: Isaac Oram <isaac.w.oram@intel.com>

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Mike Kinney <michael.d.kinney@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Mohamed Abbas <mohamed.abbas@intel.com>
Cc: Michael Kubacki <michael.kubacki@microsoft.com>
Cc: Zachary Bobroff <zacharyb@ami.com>
Cc: Harikrishna Doppalapudi <harikrishnad@ami.com>
Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
Reviewed-by: Isaac Oram <isaac.w.oram@intel.com>

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Mike Kinney <michael.d.kinney@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Mohamed Abbas <mohamed.abbas@intel.com>
Cc: Michael Kubacki <michael.kubacki@microsoft.com>
Cc: Zachary Bobroff <zacharyb@ami.com>
Cc: Harikrishna Doppalapudi <harikrishnad@ami.com>
Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
Reviewed-by: Isaac Oram <isaac.w.oram@intel.com>

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Mike Kinney <michael.d.kinney@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Mohamed Abbas <mohamed.abbas@intel.com>
Cc: Michael Kubacki <michael.kubacki@microsoft.com>
Cc: Zachary Bobroff <zacharyb@ami.com>
Cc: Harikrishna Doppalapudi <harikrishnad@ami.com>
Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
Reviewed-by: Isaac Oram <isaac.w.oram@intel.com>

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Mike Kinney <michael.d.kinney@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Mohamed Abbas <mohamed.abbas@intel.com>
Cc: Michael Kubacki <michael.kubacki@microsoft.com>
Cc: Zachary Bobroff <zacharyb@ami.com>
Cc: Harikrishna Doppalapudi <harikrishnad@ami.com>
Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
Reviewed-by: Isaac Oram <isaac.w.oram@intel.com>

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Mike Kinney <michael.d.kinney@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Mohamed Abbas <mohamed.abbas@intel.com>
Cc: Michael Kubacki <michael.kubacki@microsoft.com>
Cc: Zachary Bobroff <zacharyb@ami.com>
Cc: Harikrishna Doppalapudi <harikrishnad@ami.com>
Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
Reviewed-by: Isaac Oram <isaac.w.oram@intel.com>

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Mike Kinney <michael.d.kinney@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Mohamed Abbas <mohamed.abbas@intel.com>
Cc: Michael Kubacki <michael.kubacki@microsoft.com>
Cc: Zachary Bobroff <zacharyb@ami.com>
Cc: Harikrishna Doppalapudi <harikrishnad@ami.com>
Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
Reviewed-by: Isaac Oram <isaac.w.oram@intel.com>

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Mike Kinney <michael.d.kinney@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Mohamed Abbas <mohamed.abbas@intel.com>
Cc: Michael Kubacki <michael.kubacki@microsoft.com>
Cc: Zachary Bobroff <zacharyb@ami.com>
Cc: Harikrishna Doppalapudi <harikrishnad@ami.com>
Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
Reviewed-by: Isaac Oram <isaac.w.oram@intel.com>

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Mike Kinney <michael.d.kinney@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Mohamed Abbas <mohamed.abbas@intel.com>
Cc: Michael Kubacki <michael.kubacki@microsoft.com>
Cc: Zachary Bobroff <zacharyb@ami.com>
Cc: Harikrishna Doppalapudi <harikrishnad@ami.com>
Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
Reviewed-by: Isaac Oram <isaac.w.oram@intel.com>

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Mike Kinney <michael.d.kinney@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Mohamed Abbas <mohamed.abbas@intel.com>
Cc: Michael Kubacki <michael.kubacki@microsoft.com>
Cc: Zachary Bobroff <zacharyb@ami.com>
Cc: Harikrishna Doppalapudi <harikrishnad@ami.com>
Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
Reviewed-by: Isaac Oram <isaac.w.oram@intel.com>

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Mike Kinney <michael.d.kinney@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Mohamed Abbas <mohamed.abbas@intel.com>
Cc: Michael Kubacki <michael.kubacki@microsoft.com>
Cc: Zachary Bobroff <zacharyb@ami.com>
Cc: Harikrishna Doppalapudi <harikrishnad@ami.com>
Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
Reviewed-by: Isaac Oram <isaac.w.oram@intel.com>

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Mike Kinney <michael.d.kinney@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Mohamed Abbas <mohamed.abbas@intel.com>
Cc: Michael Kubacki <michael.kubacki@microsoft.com>
Cc: Zachary Bobroff <zacharyb@ami.com>
Cc: Harikrishna Doppalapudi <harikrishnad@ami.com>
Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
Reviewed-by: Isaac Oram <isaac.w.oram@intel.com>

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Mike Kinney <michael.d.kinney@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Mohamed Abbas <mohamed.abbas@intel.com>
Cc: Michael Kubacki <michael.kubacki@microsoft.com>
Cc: Zachary Bobroff <zacharyb@ami.com>
Cc: Harikrishna Doppalapudi <harikrishnad@ami.com>
Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
Reviewed-by: Isaac Oram <isaac.w.oram@intel.com>

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Mike Kinney <michael.d.kinney@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Mohamed Abbas <mohamed.abbas@intel.com>
Cc: Michael Kubacki <michael.kubacki@microsoft.com>
Cc: Zachary Bobroff <zacharyb@ami.com>
Cc: Harikrishna Doppalapudi <harikrishnad@ami.com>
Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
Reviewed-by: Isaac Oram <isaac.w.oram@intel.com>

With all the refactoring done during code review, I misplaced
the MAX_VARIABLE_NAME_PAD_SIZE macro. This patch adds it back.

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Michael Kubacki <michael.kubacki@microsoft.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
Reviewed-by: Michael Kubacki <michael.kubacki@microsoft.com>

Now that we are doing SoC detection and adjusting the DMA
window it should be safe to turn DMA on by default.

Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
Reviewed-by: Pete Batard <pete@akeo.ie>

The newer BCM2711 SoC's don't have a DMA constraint on the emmc2
controller. So we don't need to do the 1G translation. Lets
allow the AML to detect the SoC revision and return a different
_DMA resource.

Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
Reviewed-by: Pete Batard <pete@akeo.ie>

Pranav Madhu authored May 11, 2021 and Sami Mujawar committed May 11, 2021

Enable ACPI CPPC mechanism for RD-N2 as defined by the ACPI
specification. The implementation uses AMU registers accessible as
Fixed-feature Hardware (FFixedHW) for monitoring the performance.
Non-secure SCMI fastchannels are used to communicate with SCP to set
the desired performance. RD-N2 platform does not support CPPC revision
1 and below. So update the _OSC method to let OSPM know about this fact.

Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
Reviewed-by: Thomas Abraham <thomas.abraham@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>

Pranav Madhu authored May 11, 2021 and Sami Mujawar committed May 11, 2021

RD-N2 platform supports two LPI states, LPI1 (Standby WFI) and LPI3
(Power-down). The cluster supports LPI2 (Power-down) state. The LPI
implementation also supports combined power state for core and cluster.

Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
Reviewed-by: Thomas Abraham <thomas.abraham@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>

Pranav Madhu authored May 11, 2021 and Sami Mujawar committed May 11, 2021

Enable ACPI CPPC mechanism for RD-V1 quad-chip platform as defined by
the ACPI specification. The implementation uses AMU registers accessible
as Fixed-feature Hardware (FFixedHW) for monitoring the performance.
Non-secure SCMI fastchannels are used to communicate with SCP to set the
desired performance. RD-V1 quad-chip platform does not support CPPC
revision 1 and below. So update the _OSC method to let OSPM know about
this fact.

Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
Reviewed-by: Thomas Abraham <thomas.abraham@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>

Pranav Madhu authored May 11, 2021 and Sami Mujawar committed May 11, 2021

RD-V1 quad-chip platform supports two LPI states, LPI1 (Standby WFI) and
LPI3 (Power-down). Add idle support for RD-V1 quad-chip platform.

Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
Reviewed-by: Thomas Abraham <thomas.abraham@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>

Pranav Madhu authored May 11, 2021 and Sami Mujawar committed May 11, 2021

Enable CPPC mechanism for RD-V1 platform as defined by the ACPI
specification. The implementation uses AMU registers accessible as
Fixed-feature Hardware (FFixedHW) for monitoring the performance.
Non-secure SCMI fastchannels are used to communicate with SCP to set
the desired performance. RD-V1 platform does not support CPPC revision
1 and below. So update the _OSC method to let OSPM know about this fact.

Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
Reviewed-by: Thomas Abraham <thomas.abraham@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>

Pranav Madhu authored May 11, 2021 and Sami Mujawar committed May 11, 2021

Add helper macros required for use with ACPI collaborative processor
performance control (CPPC). This patch adds macros for initializing ACPI
_CPC and _PSD control method. The CPC initializer macro initializes _CPC
control method with revision 3 as specified in Arm FFH specification
1.1. The CPC initilizer exposes the reference performance counter and
delivered perfrmance counter (AMU registers) as FFixedHW registers. The
initilizer also expose the fastchannel memories for performance level
set performance limit set protocols as desired performance register and
performance limited register respectively.

Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
Reviewed-by: Thomas Abraham <thomas.abraham@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>

Pranav Madhu authored May 11, 2021 and Sami Mujawar committed May 11, 2021

RD-V1 platform supports 2 LPI states, LPI1 (Standby WFI) and LPI3
(Power-down). Add idle support for RD-V1 platform.

Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
Reviewed-by: Thomas Abraham <thomas.abraham@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>

Pranav Madhu authored May 11, 2021 and Sami Mujawar committed May 11, 2021

RD-N1-Edge platform in multi chip configuration supports 2 LPI states,
LPI1 (Standby WFI) and LPI3 (Power-down). The cluster supports LPI2
(Power-down) state. The LPI implementation also supports combined power
state for core and cluster.

Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
Reviewed-by: Thomas Abraham <thomas.abraham@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>

Pranav Madhu authored May 11, 2021 and Sami Mujawar committed May 11, 2021

RD-N1-Edge platform supports 2 LPI states, LPI1 (Standby WFI) and LPI3
(Power-down) and the cluster supports LPI2 (Power-down) state. The LPI
implementation also supports combined power state for core and cluster.

Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
Reviewed-by: Thomas Abraham <thomas.abraham@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>

Pranav Madhu authored May 11, 2021 and Sami Mujawar committed May 11, 2021

SGI-575 platform supports 2 LPI states, LPI1 (Standby WFI) and LPI3
(Power-down) and the cluster supports LPI2 (Power-down) state. The LPI
implementation also supports combined power state for core and cluster.

Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
Reviewed-by: Thomas Abraham <thomas.abraham@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>

Pranav Madhu authored May 11, 2021 and Sami Mujawar committed May 11, 2021

Add helper macros required for use with ACPI Operating System
Capabilities (_OSC) control method. The macros for capability DWORD and
return status value DWORD are defined.

Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
Reviewed-by: Thomas Abraham <thomas.abraham@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>

Pranav Madhu authored May 11, 2021 and Sami Mujawar committed May 11, 2021

The RD-N2 platform includes sixteen single-thread CPUS. Each of the
CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache and 1MB L2
cache. The platform also includes a system level cache of 32MB. Add PPTT
table for RD-N2 platform with this information.

Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
Reviewed-by: Thomas Abraham <thomas.abraham@arm.com>
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>

Pranav Madhu authored May 11, 2021 and Sami Mujawar committed May 11, 2021

The RD-N2 platform is a sixteen core platform with each core contained
in a minimal cluster logic. Update the processor device entries
accordingly in the DSDT ACPI table by moving each of the processor
device entries into a separate processor container devices.

Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
Reviewed-by: Thomas Abraham <thomas.abraham@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>

Pranav Madhu authored May 11, 2021 and Sami Mujawar committed May 11, 2021

The RD-V1 quad-chip platform consists of four chips connected over cache
coherent interconnect. Each chip on the platform includes four single-
thread CPUS. Each of the CPUs include 64KB L1 Data cache, 64KB L1
Instruction cache and 1MB L2 cache. The platform also includes a system
level cache of 16MB per chip. Add PPTT table for RD-V1 quad-chip
platform with this information.

Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
Reviewed-by: Thomas Abraham <thomas.abraham@arm.com>
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>

Pranav Madhu authored May 11, 2021 and Sami Mujawar committed May 11, 2021

The RD-V1 quad-chip platform is composed of four RD-V1 platforms
connected over a coherent link. Each chip has four CPU cores with each
core contained in a minimal cluster logic. Update the processor device
entries accordingly in the DSDT ACPI table by moving each of the
processor device entries into a separate processor container devices.

Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
Reviewed-by: Thomas Abraham <thomas.abraham@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>

Pranav Madhu authored May 11, 2021 and Sami Mujawar committed May 11, 2021

The RD-V1 platform includes sixteen single-thread CPUs. Each of the
CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache and 1MB
L2 cache. The platform also includes a system level cache of 16MB.
Add PPTT table for RD-V1 platform with this information.

Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
Reviewed-by: Thomas Abraham <thomas.abraham@arm.com>
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>

Pranav Madhu authored May 11, 2021 and Sami Mujawar committed May 11, 2021

The RD-V1 platform is a sixteen core platform with each core contained
in a minimal cluster logic. Update the processor device entries
accordingly in the DSDT ACPI table by moving each of the processor
device entries into a separate processor container device.

Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
Reviewed-by: Thomas Abraham <thomas.abraham@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>

Pranav Madhu authored May 11, 2021 and Sami Mujawar committed May 11, 2021

The RD-E1-Edge platform includes two clusters with eight multi-thread
CPUs. Each of the CPUs include 32KB L1 Data cache, 32KB L1 Instruction
cache and 256KB L2 cache. Each cluster includes a 2MB L3 cache. The
platform also includes a system level cache of 8MB. Add PPTT table for
RD-E1-Edge platform with this information.

Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
Reviewed-by: Thomas Abraham <thomas.abraham@arm.com>
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>

Pranav Madhu authored May 11, 2021 and Sami Mujawar committed May 11, 2021

The RD-N1-Edge dual-chip platform includes two RD-N1-Edge single-chip
platforms connected over cache coherent interconnect. Each of the
RD-N1-Edge single-chip platform includes two clusters with four
single-thread CPUs. Each of the CPUs include 64KB L1 Data cache, 64KB
L1 Instruction cache and 512KB L2 cache. Each cluster includes a 2MB
L3 cache. The platform also includes a system level cache of 8MB per
chip. Add PPTT table for RD-N1-Edge dual-chip platform with this
information.

Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
Reviewed-by: Thomas Abraham <thomas.abraham@arm.com>
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>

Pranav Madhu authored May 11, 2021 and Sami Mujawar committed May 11, 2021

The RD-N1-Edge dual-chip platform is composed of two RD-N1-Edge
platforms connected over a coherent link. Each chip has two clusters
with four CPUs in each cluster. Add the Differentiated System
Description Table (DSDT) ACPI table for this platform with processor
container devices defined containing the corresponding processor
devices.

Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>