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  1. Dec 20, 2019
  2. Dec 18, 2019
  3. Dec 17, 2019
    • Alexander Shishkin's avatar
      perf/x86/intel: Fix PT PMI handling · 92ca7da4
      Alexander Shishkin authored
      
      
      Commit:
      
        ccbebba4 ("perf/x86/intel/pt: Bypass PT vs. LBR exclusivity if the core supports it")
      
      skips the PT/LBR exclusivity check on CPUs where PT and LBRs coexist, but
      also inadvertently skips the active_events bump for PT in that case, which
      is a bug. If there aren't any hardware events at the same time as PT, the
      PMI handler will ignore PT PMIs, as active_events reads zero in that case,
      resulting in the "Uhhuh" spurious NMI warning and PT data loss.
      
      Fix this by always increasing active_events for PT events.
      
      Fixes: ccbebba4 ("perf/x86/intel/pt: Bypass PT vs. LBR exclusivity if the core supports it")
      Reported-by: default avatarVitaly Slobodskoy <vitaly.slobodskoy@intel.com>
      Signed-off-by: default avatarAlexander Shishkin <alexander.shishkin@linux.intel.com>
      Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
      Acked-by: default avatarAlexey Budankov <alexey.budankov@linux.intel.com>
      Cc: Jiri Olsa <jolsa@kernel.org>
      Cc: Ingo Molnar <mingo@redhat.com>
      Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
      Link: https://lkml.kernel.org/r/20191210105101.77210-1-alexander.shishkin@linux.intel.com
      92ca7da4
    • Alexander Shishkin's avatar
      perf/x86/intel/bts: Fix the use of page_private() · ff61541c
      Alexander Shishkin authored
      
      
      Commit
      
        8062382c ("perf/x86/intel/bts: Add BTS PMU driver")
      
      brought in a warning with the BTS buffer initialization
      that is easily tripped with (assuming KPTI is disabled):
      
      instantly throwing:
      
      > ------------[ cut here ]------------
      > WARNING: CPU: 2 PID: 326 at arch/x86/events/intel/bts.c:86 bts_buffer_setup_aux+0x117/0x3d0
      > Modules linked in:
      > CPU: 2 PID: 326 Comm: perf Not tainted 5.4.0-rc8-00291-gceb9e77324fa #904
      > RIP: 0010:bts_buffer_setup_aux+0x117/0x3d0
      > Call Trace:
      >  rb_alloc_aux+0x339/0x550
      >  perf_mmap+0x607/0xc70
      >  mmap_region+0x76b/0xbd0
      ...
      
      It appears to assume (for lost raisins) that PagePrivate() is set,
      while later it actually tests for PagePrivate() before using
      page_private().
      
      Make it consistent and always check PagePrivate() before using
      page_private().
      
      Fixes: 8062382c ("perf/x86/intel/bts: Add BTS PMU driver")
      Signed-off-by: default avatarAlexander Shishkin <alexander.shishkin@linux.intel.com>
      Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
      Cc: Jiri Olsa <jolsa@kernel.org>
      Cc: Vince Weaver <vincent.weaver@maine.edu>
      Cc: Ingo Molnar <mingo@redhat.com>
      Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
      Link: https://lkml.kernel.org/r/20191205142853.28894-2-alexander.shishkin@linux.intel.com
      ff61541c
    • Peter Zijlstra's avatar
      perf/x86: Fix potential out-of-bounds access · 1e69a0ef
      Peter Zijlstra authored
      
      
      UBSAN reported out-of-bound accesses for x86_pmu.event_map(), it's
      arguments should be < x86_pmu.max_events. Make sure all users observe
      this constraint.
      
      Reported-by: default avatarMeelis Roos <mroos@linux.ee>
      Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
      Tested-by: default avatarMeelis Roos <mroos@linux.ee>
      1e69a0ef
    • Jan H. Schönherr's avatar
      x86/mce: Fix possibly incorrect severity calculation on AMD · a3a57dda
      Jan H. Schönherr authored
      
      
      The function mce_severity_amd_smca() requires m->bank to be initialized
      for correct operation. Fix the one case, where mce_severity() is called
      without doing so.
      
      Fixes: 6bda529e ("x86/mce: Grade uncorrected errors for SMCA-enabled systems")
      Fixes: d28af26f ("x86/MCE: Initialize mce.bank in the case of a fatal error in mce_no_way_out()")
      Signed-off-by: default avatarJan H. Schönherr <jschoenh@amazon.de>
      Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
      Reviewed-by: default avatarTony Luck <tony.luck@intel.com>
      Cc: "H. Peter Anvin" <hpa@zytor.com>
      Cc: Ingo Molnar <mingo@kernel.org>
      Cc: linux-edac <linux-edac@vger.kernel.org>
      Cc: <stable@vger.kernel.org>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: x86-ml <x86@kernel.org>
      Cc: Yazen Ghannam <Yazen.Ghannam@amd.com>
      Link: https://lkml.kernel.org/r/20191210000733.17979-4-jschoenh@amazon.de
      a3a57dda
    • Yazen Ghannam's avatar
      x86/MCE/AMD: Allow Reserved types to be overwritten in smca_banks[] · 966af209
      Yazen Ghannam authored
      
      
      Each logical CPU in Scalable MCA systems controls a unique set of MCA
      banks in the system. These banks are not shared between CPUs. The bank
      types and ordering will be the same across CPUs on currently available
      systems.
      
      However, some CPUs may see a bank as Reserved/Read-as-Zero (RAZ) while
      other CPUs do not. In this case, the bank seen as Reserved on one CPU is
      assumed to be the same type as the bank seen as a known type on another
      CPU.
      
      In general, this occurs when the hardware represented by the MCA bank
      is disabled, e.g. disabled memory controllers on certain models, etc.
      The MCA bank is disabled in the hardware, so there is no possibility of
      getting an MCA/MCE from it even if it is assumed to have a known type.
      
      For example:
      
      Full system:
      	Bank  |  Type seen on CPU0  |  Type seen on CPU1
      	------------------------------------------------
      	 0    |         LS          |          LS
      	 1    |         UMC         |          UMC
      	 2    |         CS          |          CS
      
      System with hardware disabled:
      	Bank  |  Type seen on CPU0  |  Type seen on CPU1
      	------------------------------------------------
      	 0    |         LS          |          LS
      	 1    |         UMC         |          RAZ
      	 2    |         CS          |          CS
      
      For this reason, there is a single, global struct smca_banks[] that is
      initialized at boot time. This array is initialized on each CPU as it
      comes online. However, the array will not be updated if an entry already
      exists.
      
      This works as expected when the first CPU (usually CPU0) has all
      possible MCA banks enabled. But if the first CPU has a subset, then it
      will save a "Reserved" type in smca_banks[]. Successive CPUs will then
      not be able to update smca_banks[] even if they encounter a known bank
      type.
      
      This may result in unexpected behavior. Depending on the system
      configuration, a user may observe issues enumerating the MCA
      thresholding sysfs interface. The issues may be as trivial as sysfs
      entries not being available, or as severe as system hangs.
      
      For example:
      
      	Bank  |  Type seen on CPU0  |  Type seen on CPU1
      	------------------------------------------------
      	 0    |         LS          |          LS
      	 1    |         RAZ         |          UMC
      	 2    |         CS          |          CS
      
      Extend the smca_banks[] entry check to return if the entry is a
      non-reserved type. Otherwise, continue so that CPUs that encounter a
      known bank type can update smca_banks[].
      
      Fixes: 68627a69 ("x86/mce/AMD, EDAC/mce_amd: Enumerate Reserved SMCA bank type")
      Signed-off-by: default avatarYazen Ghannam <yazen.ghannam@amd.com>
      Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
      Cc: "H. Peter Anvin" <hpa@zytor.com>
      Cc: Ingo Molnar <mingo@kernel.org>
      Cc: linux-edac <linux-edac@vger.kernel.org>
      Cc: <stable@vger.kernel.org>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Tony Luck <tony.luck@intel.com>
      Cc: x86-ml <x86@kernel.org>
      Link: https://lkml.kernel.org/r/20191121141508.141273-1-Yazen.Ghannam@amd.com
      966af209
    • Konstantin Khlebnikov's avatar
      x86/MCE/AMD: Do not use rdmsr_safe_on_cpu() in smca_configure() · 246ff09f
      Konstantin Khlebnikov authored
      
      
      ... because interrupts are disabled that early and sending IPIs can
      deadlock:
      
        BUG: sleeping function called from invalid context at kernel/sched/completion.c:99
        in_atomic(): 1, irqs_disabled(): 1, non_block: 0, pid: 0, name: swapper/1
        no locks held by swapper/1/0.
        irq event stamp: 0
        hardirqs last  enabled at (0): [<0000000000000000>] 0x0
        hardirqs last disabled at (0): [<ffffffff8106dda9>] copy_process+0x8b9/0x1ca0
        softirqs last  enabled at (0): [<ffffffff8106dda9>] copy_process+0x8b9/0x1ca0
        softirqs last disabled at (0): [<0000000000000000>] 0x0
        Preemption disabled at:
        [<ffffffff8104703b>] start_secondary+0x3b/0x190
        CPU: 1 PID: 0 Comm: swapper/1 Not tainted 5.5.0-rc2+ #1
        Hardware name: GIGABYTE MZ01-CE1-00/MZ01-CE1-00, BIOS F02 08/29/2018
        Call Trace:
         dump_stack
         ___might_sleep.cold.92
         wait_for_completion
         ? generic_exec_single
         rdmsr_safe_on_cpu
         ? wrmsr_on_cpus
         mce_amd_feature_init
         mcheck_cpu_init
         identify_cpu
         identify_secondary_cpu
         smp_store_cpu_info
         start_secondary
         secondary_startup_64
      
      The function smca_configure() is called only on the current CPU anyway,
      therefore replace rdmsr_safe_on_cpu() with atomic rdmsr_safe() and avoid
      the IPI.
      
       [ bp: Update commit message. ]
      
      Signed-off-by: default avatarKonstantin Khlebnikov <khlebnikov@yandex-team.ru>
      Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
      Reviewed-by: default avatarYazen Ghannam <yazen.ghannam@amd.com>
      Cc: "H. Peter Anvin" <hpa@zytor.com>
      Cc: Ingo Molnar <mingo@redhat.com>
      Cc: linux-edac <linux-edac@vger.kernel.org>
      Cc: <stable@vger.kernel.org>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Tony Luck <tony.luck@intel.com>
      Cc: x86-ml <x86@kernel.org>
      Link: https://lkml.kernel.org/r/157252708836.3876.4604398213417262402.stgit@buzz
      246ff09f
    • Marcus Comstedt's avatar
      KVM: PPC: Book3S HV: Fix regression on big endian hosts · 228b607d
      Marcus Comstedt authored
      
      
      VCPU_CR is the offset of arch.regs.ccr in kvm_vcpu.
      arch/powerpc/include/asm/kvm_host.h defines arch.regs as a struct
      pt_regs, and arch/powerpc/include/asm/ptrace.h defines the ccr field
      of pt_regs as "unsigned long ccr".  Since unsigned long is 64 bits, a
      64-bit load needs to be used to load it, unless an endianness specific
      correction offset is added to access the desired subpart.  In this
      case there is no reason to _not_ use a 64 bit load though.
      
      Fixes: 6c85b7bc ("powerpc/kvm: Use UV_RETURN ucall to return to ultravisor")
      Cc: stable@vger.kernel.org # v5.4+
      Signed-off-by: default avatarMarcus Comstedt <marcus@mc.pp.se>
      Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
      Link: https://lore.kernel.org/r/20191215094900.46740-1-marcus@mc.pp.se
      228b607d
  4. Dec 16, 2019
  5. Dec 15, 2019
  6. Dec 14, 2019
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