Integrate RISC-V support (#477)

* Add support for the RISC-V Vector ISA
- RISC-V V 1.0 with (latest) intrinsics >=0.12.
- Enable bit manip extensions on RISC-V.
- Add RVVM*NOFMA configurations for determinism/bit-reproducibility across all architectures.

* Not supported yet
- DFT, QUAD, and GNUABI.
- Only upcoming versions of gcc (14+) have support for latest intrinsics. Will be supported when available in release version of gcc.

* CI Updates
- Add riscv64 CI on GitHub Actions.
- Add gcc (11 - #483) and llvm (17) builds on all architectures.
- Disable a few failing test variants, tracked in #484 and #485.
- Use same compiler versions across all builds.
- Add sysroot for dependencies.
- Nit: Reorder build-cross targets to group gcc/llvm per-arch together.

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Co-authored-by: GlassOfWhiskey <iacopo.c92@gmail.com>
Co-authored-by: Eric Love <eric.love@sifive.com>