LAN91C111: Includes various fixes

* Read Phy Status Out register at init to deassert them
* Ensure the correct MAC register bank is selected when enabling Transmission at init
* Drive the MDO pin correctly
* Ensure MMU cmd are correctly issued
* Return the correct status of the operation to allocate TX memory
* Advertise capabilities before setting the PHY speed
* Issue the correct value to reset the PHY
* Enable Chip ID revision check as it was confirmed that the FVP implementation
  does implement the content of the MAC Revision register
* Correct Bank select register bit mask
* Correctly Bank select register bit setting
* Remove CRC processing in Tx and Rx
* Correctly process Rx data
* Correctly auto increment the Tx Fifo on transmit

Signed-off-by: Hugues Kamba-Mpiana <hugues.kambampiana@arm.com>