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  1. Mar 04, 2019
  3. Feb 25, 2019
  5. Feb 12, 2019
  7. Feb 11, 2019
  9. Feb 08, 2019
  11. Jan 30, 2019
  13. Jan 28, 2019
  15. Jan 25, 2019
  17. Jan 24, 2019
    • Sandrine Bailleux's avatar
      Dump some registers when hitting an unexpected exception · a43b003a
      Sandrine Bailleux authored 
      

At the moment, no information is printed on the UART whenever we hit
an unexpected exception, not even an error message. This is not great
from the user's perspective, who has got no idea of what is going on.

Now we print an error message, as well as the state of some of the
registers. This includes general-purpose registers, as well as some
system registers.

This is implemented for TFTF running:

- in AArch64 state, at EL2;
- in AArch64 state, at NS-EL1;
- in AArch32 state.

We might want to dump more registers in the future but this patch
at least provides a basis we can build upon.

Also, the SP_EL0 has been removed from the list of registers saved in
the CPU context because TFTF always uses SP_ELx and does not touch
SP_EL0 at all.

Change-Id: I56e4afa917b53b5ccccff1d5d09ac8ccfaa6ae49
Signed-off-by: Sandrine Bailleux's avatarSandrine Bailleux <sandrine.bailleux@arm.com>
      a43b003a
    • Sandrine Bailleux's avatar
      Improve readability of TFTF exceptions code · e760449e
      Sandrine Bailleux authored 
      

The only exceptions that TFTF expects are IRQs from the current
exception level. All other exceptions are unhandled and put the TFTF
into an irrecoverable state. Introduce an unhandled_exception macro
that makes it clearer.

Change-Id: Ia64600d540007a648c14d8663c91c60c8591eae6
Signed-off-by: Sandrine Bailleux's avatarSandrine Bailleux <sandrine.bailleux@arm.com>
      e760449e
  19. Jan 23, 2019
  21. Jan 18, 2019
    • Sandrine Bailleux's avatar
      Use lock-less printf() in assert macro · 971545c3
      Sandrine Bailleux authored 
      

This allows to use assertions in interrupt context (which we do in
some places currently). Before this patch, a CPU could dead lock
itself by:

1. acquiring the printf lock in the normal execution context;
2. taking an interrupt while still holding the lock;
3. inside the interrupt handler, executing an assertion check that
   fails and thus tries to print an error message on the UART.

In a situation where several CPUs might be executing assert() at the
same time, we will now get interleaved messages but that should be
pretty rare.

Change-Id: I6d1603300f6a3ea5756a46338cb950b7ca3e7956
Signed-off-by: Sandrine Bailleux's avatarSandrine Bailleux <sandrine.bailleux@arm.com>
      971545c3
  23. Jan 15, 2019
    • Sandrine Bailleux's avatar
      Always print file and line number in panic/unreachable macros · a2d516fc
      Sandrine Bailleux authored 
      

Release builds used to have a special variant of these macros without
the source code location information. This kind of mechanism is useful
when writing software that needs both a development and production
version so that the source code information is not leaked when the
device is in the field.

However, in the context of TF-A Tests, it makes little sense, as it's
unlikely somebody would ever ship a device with TF-A Tests installed
on it.

Change-Id: Ic14ad87c2756762807ee71142f21d6973233144e
Signed-off-by: Sandrine Bailleux's avatarSandrine Bailleux <sandrine.bailleux@arm.com>
      a2d516fc
    • Sandrine Bailleux's avatar
      Merge changes from topic "sb/exceptions" · c1617386
      Sandrine Bailleux authored 
      * changes:
  Rework IRQ vector code
  Add CFI debug info to vector entries
  Improve readability of exceptions stubs code
  Fix comments in AArch64 exceptions code
      c1617386
    • Sandrine Bailleux's avatar
      Move unstable tests to a separate pool of tests · 3951dd90
      Sandrine Bailleux authored 
      

Some tests have proven unreliable over time. They often time out and the
root cause of the problem is unknown as of today.

This root cause needs to be investigated and fixed but until then, this
patch isolates these tests in their own pool. This allows us to set
different trust levels in our CI:
 - The stable tests are trusted to call out the validity of a patch.
 - The unstable tests are only informative.

Change-Id: Ia8ebb5a29a523ef3a1f324dbd3ddddac02254fd8
Signed-off-by: Sandrine Bailleux's avatarSandrine Bailleux <sandrine.bailleux@arm.com>
      3951dd90
  25. Jan 14, 2019
  27. Jan 11, 2019
  29. Jan 07, 2019
  31. Jan 04, 2019
  33. Jan 03, 2019
  35. Dec 21, 2018
    • Sandrine Bailleux's avatar
      Merge changes from topic "sb/terse-output" · 485cee0e
      Sandrine Bailleux authored 
      * changes:
  Remove redundant error message in tftf_initialise_timer()
  Remove prints from VExpress NOR flash driver
  Remove prints in get_overall_test_result()
  Remove SHELL_COLOR build flag
  Do not print CPU MPID in mp_printf()
  Use vprintf() inside mp_printf()
  Add vprintf() in standard C library
      485cee0e
  37. Dec 20, 2018
    • Sandrine Bailleux's avatar
      Fix waitus() · ba7695b3
      Sandrine Bailleux authored 
      

waitus() was missing an instruction barrier before reading the system
counter value. As a result, the CPU could speculatively read it and
we would potentially base our delay loop on stale values.

waitus() now uses the syscounter_read() helper function introduced in
the previous patch, which has the required ISB.

Change-Id: Ic37254485a9cdc4d4d2c86d245aa3273454e82ff
Signed-off-by: Sandrine Bailleux's avatarSandrine Bailleux <sandrine.bailleux@arm.com>
      ba7695b3