Change-Id: If1447c63ff985ce8fdaeef0c4939dbacff99a5ee
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

Change-Id: I33f4ef5707641a4a7dc597c3c9bf6c2c82111d65
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Update the user guide to reflect the correct flags needed
for the manual tests.

Change-Id: I5459e06f26f25e0f269c75adce1ec3a23f64e809
Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>

* changes:
  SPM-MM: Re-enable disabled tests
  SPM-MM: Fix call preemption test

The tests are actually passing now.

Change-Id: I0f9ef11dabded51daf791c42ce0e22ff222425db
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

The timer was being set up for 1 ms rather than 1 second.

Change-Id: I16d6ea69d42abf28dc9591e97d6bfb302d5f8127
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

* changes:
  Add ARMv8.3 pointer authentication support
  Remove pointer authentication test

The code has been taken from commit 99f4fd28 ("cactus: Use UART2
instead of UART0") and modified slightly to be integrated in the current
master.

There are three tests that are failing in the CI. They have been
disabled for the time being:

- mem_attr_changes_tests() in cactus_main() in the file
  spm/cactus_mm/cactus_mm_main.c.

- Two tests in the file tftf/tests/tests-spm-mm.xml.

Change-Id: I6332cbff1cefeb82b9447fae1b613879e65186a1
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Manual tests require setting USE_NVM=1 and NEW_TEST_SESSION=0
otherwise they will not function properly (as test results will
not be preserved across reboots). We should check that these
variables have the required values during the build.

Change-Id: I72fc8a4badf107fe2ebd6bfb88631828e14a77b3
Signed-off-by: Paul Beesley <paul.beesley@arm.com>

The FWU test components are being built as part of the
tests-standard.mk configuration but tests-standard does not
actually run any FWU tests (see tests-standard.xml). These FWU
test components do not need to be built.

Change-Id: I11a9012fcf79f4066947b0b2801c64d053f38d42
Signed-off-by: Paul Beesley <paul.beesley@arm.com>

These tests require build variables to be set to non-default values
(USE_NVM=1 and NEW_TEST_SESSION=0). This conflicts with other tests that
are part of tests-standard (the default set of tests) and so the
proposed solution is to remove them from this set.

Change-Id: Id54148aab9410002dace33ad595ac1b0cf4678ca
Signed-off-by: Paul Beesley <paul.beesley@arm.com>

ARMv8.3-PAuth adds functionality that supports address authentication of
the contents of a register before that register is used as the target of
an indirect branch, or as a load.

This feature is supported only in AArch64 state.

This feature is mandatory in ARMv8.3 implementations.

This patch adds the functionality needed for platforms to provide
authentication keys for the TF-A Test Framework, and a new option
(ENABLE_PAUTH) to enable pointer authentication in the framework itself.
This option is disabled by default.

Pointer authentication support has been added to FVP.

Change-Id: Id2d5c978deb68ae60107879f1c3d0b231cba9f42
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

This test only makes sure that the pointer authentication registers can
be read, which isn't a useful test now that the TFTF is going to support
using pointer authentication.

Change-Id: I01735677353ab08ba26f6faad1b900d98654c0d2
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Chandni Cherukuri authored Jan 08, 2019 and Sandrine Bailleux committed Mar 05, 2019

FVP_RD_N1Edge is the Fixed Virtual Platform on which the
Trusted Firmware-A Tests are executed for RD-N1-Edge

Change-Id: If6ffaa5430b9d41caf6d0697896bc92114e9a87c
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>

Ambroise Vincent authored Feb 11, 2019 and Sandrine Bailleux committed Mar 04, 2019

Added includes and sources of libc to the makefiles.

Change-Id: I8e84db9634e0df7d51caa5c5858311672dd3a8d1
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>

Ambroise Vincent authored Feb 11, 2019 and Sandrine Bailleux committed Mar 04, 2019

Reflect the changes in the structure of libc.

NB: the include of stdarg.h in nvm_results_helpers.c is not in alphabetical
order because it needs to be included before stdio.h. Fixing this would require
further changes.

Change-Id: I07f62a3450802833408ff3e1f950fd3b643e5e33
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>

Ambroise Vincent authored Feb 11, 2019 and Sandrine Bailleux committed Mar 04, 2019

Add support for functions used in TFTF but not in TF-A.

Replaced calls to plat_panic_handler with calls to panic, since there is no
implementation of the former in TFTF.

Change-Id: Ic10de2c6e749db97b932cd7ffbb6067b5befe914
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>

Keep uuid, rand and strncpy for compatibility reasons

Change-Id: Iefd82a5c9df48f6159732027e40a58f7d6afc09f
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>

Based on arm-trusted-firware commit 873e394b3bf93214a441f9f98237b58fbbea55aa

Change-Id: I510e092f2b9ff333e9461bdde8d80ed1fab1460c
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>

RD-N1-Edge platform consists of two clusters of four CPUs
each. CPU0 of the first cluster is the primary CPU. SoC UART0 is
used for the console log.

Change-Id: I724c772f95d590154536e7bc1544976e55b983cf
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>

RD-N1-Edge platform consists of two clusters of four CPU's
each. The FVP for this platform does not support system suspend and
resume functionality as there is no wakeup source supported. So all
the system suspend and resume related tests are skipped.

Change-Id: I33649c7c67023127e736c760bf0ec4193c95ed1a
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>

Change-Id: Iee1998b9b039dfd21a3ef38c5afeae3fc65569c2
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>

Change-Id: Ieb56d0639efd29c2695751b2b36cc98ce2c90dab
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Manual tests now rely on passing a flag to dump the flash to a file,
then passing that flash file back in when relaunching the model to
continue the tests.

Change-Id: I77d226b9a1d50f16fd3b13e1254f5152293b23bf
Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>

SMCCC v2.0 is no longer required for SPM, and won't be needed in the
future.

The SPM implementation based on SPCI and SPRT was using it, but it has
been adapted to SMCCC v1.0.

Change-Id: I624b32f9547274b50add4ea81b485cc9f5121e53
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

* changes:
  Dump some registers when hitting an unexpected exception
  Improve readability of TFTF exceptions code

Antonio Nino Diaz authored Jan 11, 2019 and Sandrine Bailleux committed Jan 25, 2019

Enforce full include path for includes.

The reason for this change is that having a global namespace for
includes isn't a good idea. It defeats one of the advantages of having
folders and it introduces problems that are sometimes subtle (because
you may not know the header you are actually including if there are two
of them with the same name).

Change-Id: I45e912b16c9fff81f50840dad7e7f90ed6637b2a
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

At the moment, no information is printed on the UART whenever we hit
an unexpected exception, not even an error message. This is not great
from the user's perspective, who has got no idea of what is going on.

Now we print an error message, as well as the state of some of the
registers. This includes general-purpose registers, as well as some
system registers.

This is implemented for TFTF running:

- in AArch64 state, at EL2;
- in AArch64 state, at NS-EL1;
- in AArch32 state.

We might want to dump more registers in the future but this patch
at least provides a basis we can build upon.

Also, the SP_EL0 has been removed from the list of registers saved in
the CPU context because TFTF always uses SP_ELx and does not touch
SP_EL0 at all.

Change-Id: I56e4afa917b53b5ccccff1d5d09ac8ccfaa6ae49
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

The only exceptions that TFTF expects are IRQs from the current
exception level. All other exceptions are unhandled and put the TFTF
into an irrecoverable state. Introduce an unhandled_exception macro
that makes it clearer.

Change-Id: Ia64600d540007a648c14d8663c91c60c8591eae6
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

* changes:
  hikey960: Fake only 1 core
  hikey960: Enable SGI
  hikey960: Enable MMU
  Hikey960 port: initial commit

This allows to use assertions in interrupt context (which we do in
some places currently). Before this patch, a CPU could dead lock
itself by:

1. acquiring the printf lock in the normal execution context;
2. taking an interrupt while still holding the lock;
3. inside the interrupt handler, executing an assertion check that
   fails and thus tries to print an error message on the UART.

In a situation where several CPUs might be executing assert() at the
same time, we will now get interleaved messages but that should be
pretty rare.

Change-Id: I6d1603300f6a3ea5756a46338cb950b7ca3e7956
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

Release builds used to have a special variant of these macros without
the source code location information. This kind of mechanism is useful
when writing software that needs both a development and production
version so that the source code information is not leaked when the
device is in the field.

However, in the context of TF-A Tests, it makes little sense, as it's
unlikely somebody would ever ship a device with TF-A Tests installed
on it.

Change-Id: Ic14ad87c2756762807ee71142f21d6973233144e
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

* changes:
  Rework IRQ vector code
  Add CFI debug info to vector entries
  Improve readability of exceptions stubs code
  Fix comments in AArch64 exceptions code

Some tests have proven unreliable over time. They often time out and the
root cause of the problem is unknown as of today.

This root cause needs to be investigated and fixed but until then, this
patch isolates these tests in their own pool. This allows us to set
different trust levels in our CI:
 - The stable tests are trusted to call out the validity of a patch.
 - The unstable tests are only informative.

Change-Id: Ia8ebb5a29a523ef3a1f324dbd3ddddac02254fd8
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

Jump straight to a function so that we are not constrained in the
32-instruction limit. Turn the code saving and restoring
general-purpose registers into a macro (as opposed to a function),
thus removing the need to save the link register before anything else.

Overall, this makes the code more straight-forward as we can more
clearly see that registers are saved from x0 to x30 (in this order)
without any magic twist.

Change-Id: Ic70ceee62bec5efc6f6b6a23a7bd4c1d6c2f8a97
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

This is based on TF-A commit 31823b6961d35a5d53e81d3bf4977ad7b2be81dd.

Add Call Frame Information assembler directives to vector entries so
that debuggers display the backtrace of functions that triggered a
synchronous exception. For example, a function triggering a data abort
will be easier to debug if the backtrace can be displayed from a
breakpoint at the beginning of the synchronous exception vector.

DS-5 needs CFI otherwise it will not attempt to display the backtrace.
Other debuggers might have other needs. These debug information are
stored in the ELF file but not in the final binary.

Change-Id: I1129419f318465049f53b5e41c304ea61fa44483
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>