- Mar 27, 2022
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Jiafei Pan authored
Add new scopes for ls1088a SoC, RDB and QDS boards. Signed-off-by:Jiafei Pan <Jiafei.Pan@nxp.com> Change-Id: I7c0018ecee3c590253cf258851a28c4dd7f9c1a1
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Jiafei Pan authored
Add new options SEPARATE_BL2_NOLOAD_REGION to separate no-loadable sections (.bss, stack, page tables) to a ram region specified by BL2_NOLOAD_START and BL2_NOLOAD_LIMIT. Signed-off-by: -
Biwen Li authored
Refine the code to be compatible with new CCN504 which is used by ls2088a. Signed-off-by:
Biwen Li <biwen.li@nxp.com> Signed-off-by:
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Jiafei Pan authored
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Biwen Li authored
Add macros as follows, - GICD_ISENABLER_1 - GICD_ISENABLER_3 - GICD_ICENABLER_1 - GICD_ICENABLER_3 Signed-off-by: -
Biwen Li authored
Support CHASSIS 3.0(such as SoC LS1088A). Signed-off-by:
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Jiafei Pan authored
Add base address definiton for Chassis 3 platforms. Signed-off-by: -
Jiafei Pan authored
Add Chassis 3 support for CAAM driver. Signed-off-by: -
Biwen Li authored
Add support for Chassis 3. Signed-off-by:
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Jiafei Pan authored
Enable DDR erratas for lx2 platforms. Signed-off-by: -
Jiafei Pan authored
Print Errata information in debug mode. Signed-off-by: -
Pankit Garg authored
Set the receiver gain to max value to recover cold temp marginality issue for phy-gen2 Signed-off-by:
Pankit Garg <pankit.garg@nxp.com> Signed-off-by:
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Jiafei Pan authored
Add new soc errata a010539 support. Signed-off-by: -
Jiafei Pan authored
Signed-off-by: -
Maninder Singh authored
New UDIMM 18ADF2G72AZ-2G6E1 has raw card ID = 0x1F Also, changing mask for raw card ID from - 0x8f -> 0x9f Changing the mask need the raw card to changed from 0x0f -> 0x1f Signed-off-by:
Maninder Singh <maninder.singh_1@nxp.com> Signed-off-by:
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Biwen Li authored
Fix build issue of mmap_add_ddr_region_dynamically(): ls_bl2_el3_setup.c:(.text.bl2_plat_preload_setup+0x28): undefined reference to mmap_add_ddr_region_dynamically Signed-off-by:
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Biwen Li authored
Replace bl2_offset with bl2_loc, and fix byte-swapping for Chassis2 SoC(s) only. Signed-off-by:
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Jiafei Pan authored
Add new scope for NXP DDR drivers and GIC drivers. Signed-off-by:
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- Mar 25, 2022
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Soby Mathew authored
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- Mar 24, 2022
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Soby Mathew authored
This patch reworks the GTSI service implementation in RMMD such that it is made internal to RMMD. This rework also lays the ground work for additional RMMD services which can be invoked from RMM. The rework renames some of the FID macros to make it more suited for adding more RMMD services. All the RMM-EL31 service SMCs are now routed via rmmd_rmm_el3_handler(). Signed-off-by:Soby Mathew <soby.mathew@arm.com> Change-Id: Ic52ca0f33b79a1fd1deefa8136f9586b088b2e07
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- Mar 23, 2022
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joannafarley-arm authored -
joannafarley-arm authored
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- Mar 22, 2022
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Manish Pandey2 authored
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Manish Pandey2 authored
* changes: feat(stm32mp1): select platform compilation either by flag or DT feat(stm32mp1-fdts): add support for STM32MP13 DK board feat(stm32mp1-fdts): add DDR support for STM32MP13 feat(stm32mp1-fdts): add st-io_policies node for STM32MP13 feat(stm32mp1): updates for STM32MP13 device tree compilation feat(stm32mp1-fdts): add DT files for STM32MP13 feat(dt-bindings): add TZC400 bindings for STM32MP13 feat(stm32mp1): add "Boot mode" management for STM32MP13 feat(stm32mp1): manage HSLV on STM32MP13 feat(stm32mp1): add sdmmc compatible in platform define feat(st-sdmmc2): allow compatible to be defined in platform code feat(stm32mp1): update IO compensation on STM32MP13 feat(stm32mp1): call pmic_voltages_init() in platform init feat(st-pmic): add pmic_voltages_init() function feat(stm32mp1): update CFG0 OTP for STM32MP13 feat(stm32mp1): usb descriptor update for STM32MP13 feat(st-clock): add clock driver for STM32MP13 feat(dt-bindings): add bindings for STM32MP13 feat(stm32mp1): get CPU info from SYSCFG on STM32MP13 feat(stm32mp1): use only one filter for TZC400 on STM32MP13 feat(stm32mp1): add a second fixed regulator feat(stm32mp1): adaptations for STM32MP13 image header feat(stm32mp1): update boot API for header v2.0 feat(stm32mp1): update IP addresses for STM32MP13 feat(stm32mp1): add part numbers for STM32MP13 feat(stm32mp1): chip rev. Z is 0x1001 on STM32MP13 feat(stm32mp1): update BACKUP_BOOT_MODE for STM32MP13 feat(stm32mp1): stm32mp_is_single_core() for STM32MP13 feat(stm32mp1): remove unsupported features on STM32MP13 feat(stm32mp1): update memory mapping for STM32MP13 feat(stm32mp1): introduce new flag for STM32MP13 feat(st): update stm32image tool for header v2
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Manish Pandey2 authored
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Manish Pandey2 authored
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Manish Pandey2 authored
* changes: fix(ufs): move nutrs assignment to ufs_init refactor(ufs): adds a function for sending command
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Yann Gautier authored
To choose either STM32MP13 or STM32MP15, one of the two flags can be set to 1 in the make command line. Or the platform selection can be done with device tree name, if it begins with stm32mp13 or stm32mp15. Change-Id: I72f42665c105b71a84b4952ef3fcd6c06ae4598c Signed-off-by:
Lionel Debieve <lionel.debieve@foss.st.com> Signed-off-by:
Yann Gautier <yann.gautier@st.com>
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Yann Gautier authored
This stm32mp135f-dk board embeds a STM32MP135F SoC (900MHz / crypto capabilities) and following peripherals: STPMIC (power delivery), 512MB DDR3L memory, SDcard, dual RMII Ethernet, display H7, RPI connector, wifi/BT murata combo, USBOTG/STM32G0/TypeC, STMIPID02/CSI OV5640. Add board DT file taken from kernel. Add fw-config files for this new board. Change-Id: I7cce1f8eb39815d7d1df79311bd7ad41061524b8 Signed-off-by: -
Nicolas Le Bayon authored
Add dedicated device tree files for STM32MP13. Add new DDR compatible for STM32MP13x. Signed-off-by:
Patrick Delaunay <patrick.delaunay@foss.st.com> Signed-off-by:
Nicolas Le Bayon <nicolas.le.bayon@st.com> Change-Id: Ib1bb9ad8cb2ab9f5f81549635d6604093aeb99d3
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Yann Gautier authored
To be able to load images with FIP and FCONF on STM32MP13, the st-io_policies has to be filled. It is a copy of the node in stm32mp15_bl2.dtsi . Change-Id: Ia15f50d1179e9b8aefe621dc5e0070ea845d6aac Signed-off-by: -
Yann Gautier authored
Add stm32mp13_bl2.dtsi files. Update compilation variables for STM32MP13. Change-Id: Ia3aa3abfe09c04c1a57541e565c212aa094e285c Signed-off-by: -
Yann Gautier authored
STM32MP13 is a single Cortex-A7 CPU, without co-processor. As for STM32MP15x SoC family, STM32MP15x SoCs come with different features, depending on SoC version. Each peripheral node is created. Some are left empty for the moment , and will be filled later on. Change-Id: I0166bb70dfa7f717e89e89883b059a5b873c4ef7 Signed-off-by: -
Yann Gautier authored
And new file stm32mp13-tzc400.h is created for STM32MP13. Change-Id: I18d6aa443d07dc42c0fff56fefb2a47632a2c0e6 Signed-off-by: -
Nicolas Toromanoff authored
Add new APIs to enter and exit "boot mode". In this mode a potential tamper won't block access or reset the secure IPs needed while boot, without this mode a dead lock may occurs. Change-Id: Iad60d4a0420ec125b842a285f73a20eb54cd1828 Signed-off-by:Nicolas Toromanoff <nicolas.toromanoff@st.com>
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Yann Gautier authored
On STM32MP13, the high speed mode for pads in low voltage is different from STM32MP15. Each peripheral supporting the feature has its own register. Special care is taken for SDMMC peripherals. The HSLV mode is enabled only if the max voltage for the pads is lower or equal to 1.8V. Change-Id: Id94d2cca17dd4aca4d764230a643b2bb9a5f3342 Signed-off-by: -
Yann Gautier authored
Add DT_SDMMC2_COMPAT define in stm32mp1_def.h file in platform. It allows the use of the compatible in platform code. Change-Id: I535ad67dd133bab59cf81881adaef42d8e88632c Signed-off-by: -
Yann Gautier authored
Put DT_SDMMC2_COMPAT under #ifndef. Keep the default value if it is not defined in platform code. Change-Id: I611baaf1fc622d33e655ee2c78d9c287baaa6a67 Signed-off-by: -
Yann Gautier authored
On STM32MP13, two new SD1 and SD2 IO compensations cells are added, for SDMMC1 and SDMMC2. They have to be managed the same way as the main compensation cell. Change-Id: Ib7aa648d65fc98e1613bfb46b0e7dd568fd21002 Signed-off-by: -
Yann Gautier authored
The nominal voltage for VDDCPU when Cortex-A7 runs at 650MHz is 1.25V on STM32MP13. VDDCORE should be set at 1.25V as well. This is necessary, as the PMIC values in its NVMEM are 1.2V. Signed-off-by:
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