- May 13, 2022
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Madhukar Pappireddy authored
* changes: feat(versal): add SMCCC call TF_A_PM_REGISTER_SGI feat(versal): add support to reset SGI
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Olivier Deprez authored
* changes: feat(sgi): enable fpregs context save and restore feat(spm_mm): add support to save and restore fp regs
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Sandrine Bailleux authored
* changes: docs(maintainers): add PSA, MHU, RSS comms code owners feat(plat/arm/fvp): enable RSS backend based measured boot feat(lib/psa): mock PSA APIs feat(drivers/measured_boot): add RSS backend feat(drivers/arm/rss): add RSS communication driver feat(lib/psa): add initial attestation API feat(lib/psa): add measured boot API feat(drivers/arm/mhu): add MHU driver
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joannafarley-arm authored* changes: fix(intel): remove unused printout fix(intel): fix configuration status based on start request style(intel): align the sequence in header file fix(intel): remove redundant NOC header declarations
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Dávid Vincze authored
Adding Sandrine Bailleux for the PSA APIs and myself for the MHU and RSS comms drivers as code owner. Change-Id: Ib948479cc6e46163aae59c938877a2d0bcf91754 Signed-off-by:David Vincze <david.vincze@arm.com>
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Sieu Mun Tang authored
This patch is to remove unused printout. Signed-off-by:Sieu Mun Tang <sieu.mun.tang@intel.com> Change-Id: I507210402dcbaf8369209308ae1fcedaccb0292d
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Sieu Mun Tang authored
This patch is to fix configuration status command now returns the result based on the last config start command made to the runtime software. The status type can be either: - NO_REQUEST (default) - RECONFIGURATION - BITSTREAM_AUTH Signed-off-by: -
Sieu Mun Tang authored
This patch is to align the sequence of function in header file. Signed-off-by: -
Sieu Mun Tang authored
This patch is to remove redundant NOC declarations in system manager header file. The NOC headers are shareable across both Stratix 10 and Agilex platforms. Signed-off-by:
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- May 12, 2022
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Tanmay Shah authored
This call is used to register and reset SGI interrupt. Before this functionality was performed using IOCTL_REGISTER_SGI pm_ioctl EEMI call. It's not correct use of PM_IOCTL as it is not EEMI functionality. Instead this new SMCCC call will be handled by TF-A specific handler. Change-Id: If2408af38b889d29a5c584e8eec5f1672eab4fb5 Signed-off-by:Tanmay Shah <tanmay.shah@xilinx.com>
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Venkatesh Yadav Abbarapu authored
Add "reset" parameter in pm_register_sgi() to reset SGI number. This will be required if OS wants to reset SGI number to default state. Caller can reset param to 1 to reset SGI in ATF. Change-Id: If485ff275df884f74eb67671cac7fa953458afe9 Signed-off-by:
Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by:
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Madhukar Pappireddy authored
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Madhukar Pappireddy authored
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Madhukar Pappireddy authored
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Madhukar Pappireddy authored
* changes: fix(intel): add flash dcache after return response for INTEL_SIP_SMC_MBOX_SEND_CMD fix(intel): extending to support large file size for SHA2/HMAC get digest and verifying fix(intel): extending to support large file size for SHA-2 ECDSA data signing and signature verifying fix(intel): extending to support large file size for AES encryption and decryption feat(intel): support version 2 SiP SVC SMC function ID for mailbox commands feat(intel): support version 2 SiP SVC SMC function ID for non-mailbox commands fix(intel): update certificate mask for FPGA Attestation feat(intel): update to support maximum response data size feat(intel): support ECDSA HASH Verification feat(intel): support ECDSA HASH Signing feat(intel): support ECDH request feat(intel): support ECDSA SHA-2 Data Signature Verification feat(intel): support ECDSA SHA-2 Data Signing feat(intel): support ECDSA Get Public Key feat(intel): support session based SDOS encrypt and decrypt feat(intel): support AES Crypt Service feat(intel): support HMAC SHA-2 MAC verify request feat(intel): support SHA-2 hash digest generation on a blob feat(intel): support extended random number generation feat(intel): support crypto service key operation feat(intel): support crypto service session feat(intel): extend attestation service to Agilex family fix(intel): flush dcache before sending certificate to mailbox fix(intel): introduce a generic response error code fix(intel): allow non-secure access to FPGA Crypto Services (FCS) feat(intel): single certificate feature enablement feat(intel): initial commit for attestation service fix(intel): update encryption and decryption command logic
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Madhukar Pappireddy authored
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- May 11, 2022
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Bipin Ravi authored
Implements the loop workaround for Cortex Makalu/Makalu-ELP/Hunter and Neoverse Demeter/Poseidon. Signed-off-by:Bipin Ravi <bipin.ravi@arm.com> Change-Id: If5f6689b662ecac92491e0c0902df4270051ce5b
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Bipin Ravi authored
DSU-110 erratum 2313941 is a Cat B erratum and applies to revisions r0p0, r1p0, r2p0, r2p1, r3p0, r3p1 and is still open. The workaround sets IMP_CLUSTERACTLR_EL1[16:15] bits to 0b11 to disable clock gating of the SCLK domain. This will increase the idle power consumption. This patch applies the fix for Cortex-X2/A510/A710 and Neoverse N2. SDEN can be found here: https://developer.arm.com/documentation/SDEN1781796/latest Signed-off-by:
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Nishant Sharma authored
This is required to prevent Nwd context corruption during StMM execution. Standalone MM uses OpenSSL for secure boot, which uses FP registers for floating point calculations. Signed-off-by:Nishant Sharma <nishant.sharma@arm.com> Change-Id: I6ed11d4fa5d64c3089a24b66fd048a841c480792
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Nishant Sharma authored
Add the support to save Nwd's floating point registers before switching to SEL0 and then restore it after coming out of it. Emit a warning message if SPM_MM is built with CTX_INCLUDE_FPREGS == 0 There is no need to save FP registers of SEL0 because secure partitions run to completion. This change is used to prevent context corruption if secure partition enabled and Nwd decide to use floating point registers. Signed-off-by: -
Madhukar Pappireddy authored
* changes: fix(st-spi): remove SR_BUSY bit check before sending command fix(st-spi): always check SR_TCF flags in stm32_qspi_wait_cmd()
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Madhukar Pappireddy authored
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Bipin Ravi authored
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Bipin Ravi authored
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Bipin Ravi authored
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Enable the RSS backend based measured boot feature. In the absence of RSS the mocked version of PSA APIs are used. They always return with success and hard-code data. Signed-off-by:Tamas Ban <tamas.ban@arm.com> Change-Id: I7543e9033a7a21f1b836d911d8d9498c6e09b956
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Introduce PLAT_RSS_NOT_SUPPORTED build config to provide a mocked version of PSA APIs. The goal is to test the RSS backend based measured boot and attestation token request integration on such a platform (AEM FVP) where RSS is otherwise unsupported. The mocked PSA API version does not send a request to the RSS, it only returns with success and hard-coded values. Signed-off-by: -
Runtime Security Subsystem (RSS) provides for the host: - Runtime service to store measurments, which were computed by the host during measured boot. Signed-off-by: -
This commit adds a driver to conduct the AP's communication with the Runtime Security Subsystem (RSS). RSS is Arm's reference implementation for the CCA HES [1]. It can be considered as a secure enclave to which, for example, certain services can be offloaded such as initial attestation. RSS comms driver: - Relies on MHU v2.x communication IP, using a generic MHU API, - Exposes the psa_call(..) API to the upper layers. [1] https://developer.arm.com/documentation/DEN0096/latest Signed-off-by:
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Supports: - Get Platform Attestation token from secure enclave Signed-off-by: -
A secure enclave could provide an alternate backend for measured boot. This API can be used to store measurements in a secure enclave, which provides the measured boot runtime service. Signed-off-by: -
The Arm Message Handling Unit (MHU) is a mailbox controller used to communicate with other processing element(s). Adding a driver to enable the communication: - Adding generic MHU driver interface, - Adding MHU_v2_x driver. Driver supports: - Discovering available MHU channels, - Sending / receiving words over MHU channels, - Signaling happens over a dedicated channel. Signed-off-by:
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Implements the loop workaround for Cortex-X1. Signed-off-by:Okash Khawaja <okash@google.com> Change-Id: I5828a26c1ec3cfb718246ea5c3b099dabc0fb3d7
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This patch adds workarounds for following cortex-x1 errata: - 1821534 (CatB) - 1688305 (CatB) - 1827429 (CatB) SDEN can be found here: https://developer.arm.com/documentation/SDEN1401782/latest Signed-off-by:
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This patch adds basic CPU library code to support Cortex-X1 CPU in TF-A. Follow-up patches will add selected errata workarounds for this CPU. Signed-off-by: -
Daniel Boulby authored
Change-Id: I72d200a0cfbcb4ef53b732faa5b7125dce91395d Signed-off-by:Daniel Boulby <daniel.boulby@arm.com>
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Sieu Mun Tang authored
This patch is to add flash dcache after return response in INTEL_SIP_SMC_MBOX_SEND_CMD. Signed-off-by: -
Sieu Mun Tang authored
This patch is to extend to support large file size for SHA2/HMAC get digest and verifying. The large file will be split into smaller chunk and send using initialize, update and finalize staging method. Signed-off-by:
Yuslaimi, Alif Zakuan <alif.zakuan.yuslaimi@intel.com> Signed-off-by:
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Sieu Mun Tang authored
fix(intel): extending to support large file size for SHA-2 ECDSA data signing and signature verifying This patch is to extend to support large file size for SHA-2 ECDSA data signing and signature verifying. The large file will be split into smaller chunk and send using initialize, update and finalize staging method. Signed-off-by: -
Sieu Mun Tang authored
This patch is to extend to support large file size for AES encryption and decryption. The large file will be split into smaller chunk and send using initialize, update and finalize staging method. Signed-off-by:
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