- Feb 02, 2022
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Manish Pandey2 authored
* changes: feat(stm32mp1): warn when debug enabled on secure chip fix(stm32mp1): rework switch/case for MISRA feat(st): disable authentication based on part_number
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Manish Pandey2 authored
* changes: fix(sptool): add leading zeroes in UUID conversion feat(tc): enable SMMU for DPU feat(tc): add reserved memory region for Gralloc feat(tc): enable GPU fix(tc): remove the bootargs node
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Madhukar Pappireddy authored
* changes: feat(st-gpio): do not apply secure config in BL2 feat(st): get pin_count from the gpio-ranges property feat(st-gpio): allow to set a gpio in output mode refactor(st-gpio): code improvements
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Anders Dellien authored
The UUID conversion drops leading zeroes, so make sure that all hex strings always are 8 digits long Signed-off-by:
Anders Dellien <anders.dellien@arm.com> Change-Id: I5d7e3cf3b53403a02bf551f35f17dbdb96dec8ae
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Manish Pandey2 authored
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- Feb 01, 2022
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Yann Gautier authored
At boot, the devices under ETZPC control are secured, so should be their GPIOs. As securable GPIOs are secured by default, keep the reset values in BL2. Change-Id: I9e560d936f8e8fda0f96f6299bb0c3b35ba9b71f Signed-off-by:
Yann Gautier <yann.gautier@st.com>
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Fabien Dessenne authored
The "ngpios" property is deprecated and may be removed. Use the "gpio-ranges" property where the last parameter of that property is the number of available pins within that range. Signed-off-by:
Fabien Dessenne <fabien.dessenne@foss.st.com> Change-Id: I28295412c7cb1246fc753cff0d447b6fdcdc4c0f
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Fabien Dessenne authored
Allow to set a gpio in output mode from the device tree. Signed-off-by:
Fabien Dessenne <fabien.dessenne@foss.st.com> Change-Id: Ic483324bc5fe916a60df05f74706bd1da4d08aa5
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Fabien Dessenne authored
No functional, change, but some improvements: - Declare set_gpio() as static (only called locally) - Handle the type ('open-drain') property independently from the mode one. - Replace mmio_clrbits_32() + mmio_setbits_32() with mmio_clrsetbits_32(). - Add a missing log - Add missing U() in macro definitions Signed-off-by:
Fabien Dessenne <fabien.dessenne@foss.st.com> Change-Id: I1a79609609ac8e8001127ebefdb81def573f76fa
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Madhukar Pappireddy authored
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Lionel Debieve authored
Add a banner that inform user that debug is enabled on a secure chip. Change-Id: Ib618ac1332b40a1af72d0b60750eea4fc36a8014 Signed-off-by:
Lionel Debieve <lionel.debieve@st.com> Signed-off-by:
Yann Gautier <yann.gautier@st.com>
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Yann Gautier authored
Avoid the use of return inside switch/case in stm32mp_is_single_core(). Although this MISRA rulre might not be enforced, we align on what is done for stm32mp_is_auth_supported(). Change-Id: I00a5ec1b18c55b4254af00c9c5cf5a4dce104175 Signed-off-by:
Yann Gautier <yann.gautier@st.com>
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Lionel Debieve authored
STM32MP15xA and STM32MP15xD chip part numbers don't support the secure boot. All functions linked to secure boot must not be used and signed binaries are not allowed on such chip. Signed-off-by:
Lionel Debieve <lionel.debieve@st.com> Change-Id: I5b85f322f5eb3b64415e1819bd00fb2c99f20695
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Anders Dellien authored
The SMMU needs to be enabled to support 8GB RAM Signed-off-by:
Anders Dellien <anders.dellien@arm.com> Change-Id: Ie81f2fc59886c52e9d6ed799ea73f49eb7a7c307
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Anders Dellien authored
Gralloc for Android S uses dmabuf, we need to add reserved memory area for these allocations Signed-off-by:
Anders Dellien <anders.dellien@arm.com> Change-Id: If869ac930fadc374ec435cae3847ba374584275b
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Anders Dellien authored
Add DTS node for GPU to support hardware rendering in Android Signed-off-by:
Anders Dellien <anders.dellien@arm.com> Change-Id: I2cf2badf5b15e59a910f6cf7d3d30fdfaf4fe9ce
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Anders Dellien authored
We need to keep the kernel command line in Yocto, otherwise we can't support AVB. Signed-off-by:
Anders Dellien <anders.dellien@arm.com> Change-Id: Ic291eb13620b307f10354c2c2797c6fc9b053e83
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- Jan 31, 2022
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Madhukar Pappireddy authored
* changes: feat(stm32mp1): manage monotonic counter feat(stm32mp1): new way to access platform OTP feat(stm32mp1-fdts): update NVMEM nodes refactor(st-drivers): improve BSEC driver feat(stm32mp1-fdts): add nvmem_layout node and OTP definitions feat(stm32mp1): add NVMEM layout compatibility definition
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Manish Pandey2 authored
* changes: fix(plat/rcar3): change stack size of BL31 fix(plat/rcar3): fix SYSTEM_OFF processing for R-Car D3
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Madhukar Pappireddy authored
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Daniel Boulby authored
Also split SPM MM into it's own scope. Change-Id: I9cfb1ddec7419ad0d7b539f65e7322bbd44a3913 Signed-off-by:
Daniel Boulby <daniel.boulby@arm.com>
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Yann Gautier authored
The monotonic counter is stored in an OTP fuse. A check is done in TF-A. If the TF-A version is incremented, then the counter will be updated in the corresponding OTP. Change-Id: I6e7831300ca9efbb35b4c87706f2dcab35affacb Signed-off-by:
Yann Gautier <yann.gautier@st.com> Signed-off-by:
Mathieu Belou <mathieu.belou@st.com>
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- Jan 28, 2022
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Lionel Debieve authored
Use dt_find_otp_name() to retrieve platform OTP information from device tree, directly or through stm32_get_otp_index() and stm32_get_otp_value() platform services. String definitions replace hard-coded values, they are used to call this new function. Change-Id: I81213e4a9ad08fddadc2c97b064ae057a4c79561 Signed-off-by:
Nicolas Le Bayon <nicolas.le.bayon@st.com> Signed-off-by:
Yann Gautier <yann.gautier@st.com>
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Nicolas Le Bayon authored
Set non-secure property on platform secure OTP nodes that non-secure world is allowed to access through secure world services. These are the SoC MAC address and the ST boards board_id OTPs. Most of these were already done but it was missing for ED1 board. Change-Id: Idfa6322d9d5c35285706d0b2d32ae09af38684a7 Signed-off-by:
Nicolas Le Bayon <nicolas.le.bayon@st.com>
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Nicolas Le Bayon authored
Rename driver file to BSEC2. Split header file in IP and feature parts. Add functions to access BSEC scratch register. Several corrections and improvements. Probe the driver earlier, especially to check debug features. Change-Id: I1981536398d598d67a19d2d7766dacc18de72ec1 Signed-off-by:
Nicolas Le Bayon <nicolas.le.bayon@st.com> Signed-off-by:
Yann Gautier <yann.gautier@st.com>
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Nicolas Le Bayon authored
A new nvmem_layout node includes nvmem platform-dependent layout information, such as OTP NVMEM cell lists (phandle, name). This list allows easy access to OTP offsets defined in BSEC node, where more OTP definitions with offsets in bytes and length have been added (replace hard-coded values). Each board may redefine this list, especially for board_id info. Change-Id: I910ae671b3bf3320ee6500fecc9ec335ae67bbda Signed-off-by:
Nicolas Le Bayon <nicolas.le.bayon@st.com> Signed-off-by:
Yann Gautier <yann.gautier@st.com>
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Nicolas Le Bayon authored
Used by driver parsing this node to get information. Change-Id: I50623a497157adf7b9da6fafe8d79f6ff58c0ebc Signed-off-by:
Nicolas Le Bayon <nicolas.le.bayon@st.com>
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Bipin Ravi authored
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Madhukar Pappireddy authored
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Pascal Paillet authored
Add support for regulator-always-on at BL2 level as it was supported before using the regulator framework. Signed-off-by:
Pascal Paillet <p.paillet@st.com> Change-Id: Idb2f4ddc2fdd4e0d31fb33da87c84618aa2e5135
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Yann Gautier authored
Correct ERROR message in scmi_process_message(). Signed-off-by:
Yann Gautier <yann.gautier@st.com> Change-Id: I55e337a3904045aa188975f6a7ed3e989678f571
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Manish Pandey2 authored
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Jayanth Dodderi Chidanand authored
This patch adds the basic CPU library code to support the Poseidon CPU in TF-A. Poseidon is derived from HunterELP core, an implementation of v9.2 architecture. Currently, Hunter CPU the predecessor to HunterELP, is supported in TF-A. Accordingly the Hunter CPU library code has been as the base and adapted here. Signed-off-by:
Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com> Change-Id: I406b4de156a67132e6a5523370115aaac933f18d
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Manish Pandey2 authored
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Yann Gautier authored
This warning can only be removed if the version is newer than v1.6.0. Signed-off-by:
Yann Gautier <yann.gautier@foss.st.com> Change-Id: I472a8e552305b563447e8148074a5c0970b429e3
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Yann Gautier authored
If a board declares an mmc1 alias in its DT and is compiled without flags STM32MP_EMMC or STM32MP_SDMMC, the DT will fail to build. Add /delete-property/ mmc1; to correct this. Signed-off-by:
Yann Gautier <yann.gautier@st.com> Change-Id: I1938ff99dc3d883f9174ee886f9ffa195ec60373
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Yann Gautier authored
Some of the ST drivers were not listed, and had no scopes. Add BSEC, Crypto, DDR, I2C, FMC, GPIO, Regulator, Reset, SPI and Watchdog. Signed-off-by:
Yann Gautier <yann.gautier@st.com> Change-Id: I4441f160f778d4bf7686e24e7d2d3c8330891327
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- Jan 27, 2022
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Manish Pandey2 authored
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Manish Pandey2 authored
* changes: refactor(st-clock): update STGEN management feat(st-clock): assign clocks to the correct BL feat(st-clock): do not refcount on non-secure clocks in bl32 feat(st-clock): define secure and non-secure gate clocks refactor(stm32mp1): remove unused refcount helper functions fix(stm32mp1): add missing debug.h refactor(st-clock): use refcnt instead of secure status
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Lionel Debieve authored
Rework STGEN config function, and move it to stm32mp_clkfunc.c file. Change-Id: I7784a79c486d1b8811f6f8d123e49ea34899e9b6 Signed-off-by:
Lionel Debieve <lionel.debieve@st.com> Signed-off-by:
Yann Gautier <yann.gautier@st.com>
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