The link to commitlintrc.js file in the v2.7 changelog
is updated.

Change-Id: I24ee736180d8df72b2d831e110a9a3a80a6d9862
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

* changes:
  fix(scmi-msg): base: fix protocol list querying
  fix(scmi-msg): base: fix protocol list response size

With recent changes, TF-A now panics on MC-1, Avenger96 and Odyssey:

  NOTICE:  CPU: STM32MP157C?? Rev.B
  NOTICE:  Model: Linux Automation MC-1 board
  ERROR:   regul ldo3: max value 750 is invalid
  PANIC at PC : 0x2ffeebb7

as the driver takes great offense at the content of the device
tree. The parts in question were copy-pasted from ST DTs, but
those ST DTs were fixed by commit 67d95409
("refactor(stm32mp1-fdts): update regulator description").

Fix the breakage by transplanting the same changes into all
remaining STM32MP1 DTs.

Change was boot-tested on MC-1, but only build tested for the
other two.

Fixes: bba9fdee ("feat(stm32mp1): add regulator framework compilation")
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Change-Id: I143d0091625f62c313b3b71449c9ad99583d01c8

Change-Id: I573e5eb3c7fad097892292c8a967dc02d72d12e6
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

* changes:
  docs(threat-model): broaden the scope of threat #05
  docs(threat-model): emphasize whether mitigations are implemented

* changes:
  docs(spm): refresh FF-A SPM design doc
  docs(spm): update FF-A manifest binding

- Move manifest binding doc as a dedicated SPM doc section.
- Highlight introduction of an EL3 FF-A SPM solution.
- Refresh TF-A build options.
- Refresh PE MMU configuration section.
- Add arch extensions for security hardening section.
- Minor corrections, typos fixes and rephrasing.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I2db06c140ef5871a812ce00a4398c663d5433bb4

- Add security state attribute to memory and device regions.
- Rename device region reg attribution to base-address aligned with
  memory regions.
- Add pages-count field to device regions.
- Refresh interrupt attributes description in device regions.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I901f48d410edb8b10f65bb35398b80f18105e427

 - Cite crash reports as an example of sensitive
   information. Previously, it might have sounded like this was the
   focus of the threat.

 - Warn about logging high-precision timing information, as well as
   conditionally logging (potentially nonsensitive) information
   depending on sensitive information.

Change-Id: I33232dcb1e4b5c81efd4cd621b24ab5ac7b58685
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

For each threat, we now separate:
 - how to mitigate against it;
 - whether TF-A currently implements these mitigations.

A new "Mitigations implemented?" box is added to each threat to
provide the implementation status. For threats that are partially
mitigated from platform code, the original text is improved to make
these expectations clearer. The hope is that platform integrators will
have an easier time identifying what they need to carefully implement
in order to follow the security recommendations from the threat model.

Change-Id: I8473d75946daf6c91a0e15e61758c183603e195b
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

* changes:
  docs(spm): update ff-a boot protocol documentation
  docs(maintainers): add code owner to sptool

Updated following sections to document implementation of the FF-A boot
information protocol:
- Describing secure partitions.
- Secure Partition Packages.
- Passing boot data to the SP.
Also updated description of the manifest field 'gp-register-num'.

Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: I5c856437b60cdf05566dd636a01207c9b9f42e61

This patch fixes the following encodings in the System register
encoding space for the MPAM registers. The encodings now match
with the Arm® Architecture Reference Manual Supplement for MPAM.

* MPAMVPM0_EL2
* MPAMVPM1_EL2
* MPAMVPM2_EL2
* MPAMVPM3_EL2
* MPAMVPM4_EL2
* MPAMVPM5_EL2
* MPAMVPM6_EL2
* MPAMVPM7_EL2
* MPAMVPMV_EL2

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Ib339412de6a9c945a3307f3f347fe7b2efabdc18

After the SRC bit clear, we must wait for a while to make sure
the operation is finished. And don't enable all the PU domains
by default.

for USB OTG, the limitations are:
1. before system clock configuration. ipg clock runs at 12.5MHz.
delay time should longer than 82us.

2. after system clock configuration. ipg clock runs at 66.5MHz.
delay time should longer than 15.3us.

so add udelay 100 to safely clear the SRC bit 0.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I52e8e7739fdaaf86442bcd148e768b6af38bcdb7

Add Joao Alves as code owner to the sptool.

Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: I9e44e322ba1cce62308bf16c4a6253f7b0117fe0

Denver CPUs use the same workaround for CVE-2017-5715 and CVE-2022-23960
vulnerabilities. The workaround for CVE-2017-5715 is always enabled, so
all Denver variants use CPU_NO_EXTRA3_FUNC as a placeholder for the
mitigation for CVE-2022-23960. This patch implements the approach.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I0863541ce19b6b3b6d1b2f901d3fb6a77f315189

* changes:
  fix(spmc): fix incorrect FF-A version usage
  fix(spmc): fix FF-A memory transaction validation

Different from other i.MX SoCs, which typically use a 24MHz reference clock,
the i.MX8MQ uses a 25MHz reference clock. As the architected timer clock
frequency is directly sourced from the reference clock via a /3 divider this
SoC runs the timers at 8.33MHz.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Change-Id: Ief36af9ffebce7cb75a200124134828d3963e744

Optimizing the pinctrl_functions structure. Remove the pointer to
array of u16 type which consumes a lot of memory (64bits pointer to
array + 16B for END_OF_GROUPS + almost useless 8bits on every entry
which is the same for every group) and add two new members of type
u16 and u8 with the name called group_base and group_size
respectively.

The group_base member contains the base value of pinctrl group whereas
the group_size member contains the total number of groups requested
from the pinctrl function.

Overall, it saves around ~2KB of RAM and ~0.7KB of code memory.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Ronak Jain <ronak.jain@xilinx.com>
Change-Id: I79b761b45df350d390fa344d411b340d9b2f13ac

Fixing possible Null pointer dereference error, found
by Coverity scan.

Change-Id: If60b7f7e13ecbc3c01e3a9c5005c480260bbabdd
Signed-off-by: David Vincze <david.vincze@arm.com>

Fix the wrong FF-A version being used for retrieving existing memory
descriptors for v1.0 clients. Internally these should always be stored
using the latest version rather than client version.

Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: Ibee1b2452c8d6ebd23bbd9d703c96ca185444093

Fix an incorrect bound check for overlapping memory regions which can
give false positives if the two regions are consecutive to each other.

Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: I997dc4d1ef2014660cc964aff0a73e348c44eff0

GCC 11 and Clang 14 now use the DWARF 5 standard by default however
Arm-DS currently only supports up to version 4. Therefore, for debug
builds, ensure the DWARF 4 standard is used.
Also update references for Arm DS-5 to it's successor Arm-DS (Arm
Development Studio).

Change-Id: Ica59588de3d121c1b795b3699f42c31f032cee49
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>

* changes:
  docs(threat-model): make measured boot out of scope
  docs(threat-model): revamp threat #9

* changes:
  feat(fvp): add plat hook for memory transactions
  feat(spmc): enable handling of the NS bit
  feat(spmc): add support for v1.1 FF-A memory data structures
  feat(spmc/mem): prevent duplicated sharing of memory regions
  feat(spmc/mem): support multiple endpoints in memory transactions
  feat(spmc): add support for v1.1 FF-A boot protocol
  feat(plat/fvp): introduce accessor function to obtain datastore
  feat(spmc/mem): add FF-A memory management code

* changes:
  feat(partition): verify crc while loading gpt header
  build(hikey): platform changes for verifying gpt header crc
  build(agilex): platform changes for verifying gpt header crc
  build(stratix10): platform changes for verifying gpt header crc
  build(stm32mp1): platform changes for verifying gpt header crc

Add call to platform hooks upon successful transmission of a
memory transaction request and as part of a memory reclaim request.
This allows for platform specific functionality to be performed
accordingly.

Note the hooks must be placed in the initial share request and final
reclaim to prevent order dependencies with operations that may take
place in the normal world without visibility of the SPMC.

Add a dummy implementation to the FVP platform.

Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: I0c7441a9fdf953c4db0651512e5e2cdbc6656c79