- Mar 22, 2022
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Manish Pandey2 authored
* changes: feat(stm32mp1): select platform compilation either by flag or DT feat(stm32mp1-fdts): add support for STM32MP13 DK board feat(stm32mp1-fdts): add DDR support for STM32MP13 feat(stm32mp1-fdts): add st-io_policies node for STM32MP13 feat(stm32mp1): updates for STM32MP13 device tree compilation feat(stm32mp1-fdts): add DT files for STM32MP13 feat(dt-bindings): add TZC400 bindings for STM32MP13 feat(stm32mp1): add "Boot mode" management for STM32MP13 feat(stm32mp1): manage HSLV on STM32MP13 feat(stm32mp1): add sdmmc compatible in platform define feat(st-sdmmc2): allow compatible to be defined in platform code feat(stm32mp1): update IO compensation on STM32MP13 feat(stm32mp1): call pmic_voltages_init() in platform init feat(st-pmic): add pmic_voltages_init() function feat(stm32mp1): update CFG0 OTP for STM32MP13 feat(stm32mp1): usb descriptor update for STM32MP13 feat(st-clock): add clock driver for STM32MP13 feat(dt-bindings): add bindings for STM32MP13 feat(stm32mp1): get CPU info from SYSCFG on STM32MP13 feat(stm32mp1): use only one filter for TZC400 on STM32MP13 feat(stm32mp1): add a second fixed regulator feat(stm32mp1): adaptations for STM32MP13 image header feat(stm32mp1): update boot API for header v2.0 feat(stm32mp1): update IP addresses for STM32MP13 feat(stm32mp1): add part numbers for STM32MP13 feat(stm32mp1): chip rev. Z is 0x1001 on STM32MP13 feat(stm32mp1): update BACKUP_BOOT_MODE for STM32MP13 feat(stm32mp1): stm32mp_is_single_core() for STM32MP13 feat(stm32mp1): remove unsupported features on STM32MP13 feat(stm32mp1): update memory mapping for STM32MP13 feat(stm32mp1): introduce new flag for STM32MP13 feat(st): update stm32image tool for header v2
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Manish Pandey2 authored
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Manish Pandey2 authored
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Manish Pandey2 authored
* changes: fix(ufs): move nutrs assignment to ufs_init refactor(ufs): adds a function for sending command
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Yann Gautier authored
To choose either STM32MP13 or STM32MP15, one of the two flags can be set to 1 in the make command line. Or the platform selection can be done with device tree name, if it begins with stm32mp13 or stm32mp15. Change-Id: I72f42665c105b71a84b4952ef3fcd6c06ae4598c Signed-off-by:
Lionel Debieve <lionel.debieve@foss.st.com> Signed-off-by:
Yann Gautier <yann.gautier@st.com>
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Yann Gautier authored
This stm32mp135f-dk board embeds a STM32MP135F SoC (900MHz / crypto capabilities) and following peripherals: STPMIC (power delivery), 512MB DDR3L memory, SDcard, dual RMII Ethernet, display H7, RPI connector, wifi/BT murata combo, USBOTG/STM32G0/TypeC, STMIPID02/CSI OV5640. Add board DT file taken from kernel. Add fw-config files for this new board. Change-Id: I7cce1f8eb39815d7d1df79311bd7ad41061524b8 Signed-off-by: -
Nicolas Le Bayon authored
Add dedicated device tree files for STM32MP13. Add new DDR compatible for STM32MP13x. Signed-off-by:
Patrick Delaunay <patrick.delaunay@foss.st.com> Signed-off-by:
Nicolas Le Bayon <nicolas.le.bayon@st.com> Change-Id: Ib1bb9ad8cb2ab9f5f81549635d6604093aeb99d3
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Yann Gautier authored
To be able to load images with FIP and FCONF on STM32MP13, the st-io_policies has to be filled. It is a copy of the node in stm32mp15_bl2.dtsi . Change-Id: Ia15f50d1179e9b8aefe621dc5e0070ea845d6aac Signed-off-by: -
Yann Gautier authored
Add stm32mp13_bl2.dtsi files. Update compilation variables for STM32MP13. Change-Id: Ia3aa3abfe09c04c1a57541e565c212aa094e285c Signed-off-by: -
Yann Gautier authored
STM32MP13 is a single Cortex-A7 CPU, without co-processor. As for STM32MP15x SoC family, STM32MP15x SoCs come with different features, depending on SoC version. Each peripheral node is created. Some are left empty for the moment , and will be filled later on. Change-Id: I0166bb70dfa7f717e89e89883b059a5b873c4ef7 Signed-off-by: -
Yann Gautier authored
And new file stm32mp13-tzc400.h is created for STM32MP13. Change-Id: I18d6aa443d07dc42c0fff56fefb2a47632a2c0e6 Signed-off-by: -
Nicolas Toromanoff authored
Add new APIs to enter and exit "boot mode". In this mode a potential tamper won't block access or reset the secure IPs needed while boot, without this mode a dead lock may occurs. Change-Id: Iad60d4a0420ec125b842a285f73a20eb54cd1828 Signed-off-by:Nicolas Toromanoff <nicolas.toromanoff@st.com>
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Yann Gautier authored
On STM32MP13, the high speed mode for pads in low voltage is different from STM32MP15. Each peripheral supporting the feature has its own register. Special care is taken for SDMMC peripherals. The HSLV mode is enabled only if the max voltage for the pads is lower or equal to 1.8V. Change-Id: Id94d2cca17dd4aca4d764230a643b2bb9a5f3342 Signed-off-by: -
Yann Gautier authored
Add DT_SDMMC2_COMPAT define in stm32mp1_def.h file in platform. It allows the use of the compatible in platform code. Change-Id: I535ad67dd133bab59cf81881adaef42d8e88632c Signed-off-by: -
Yann Gautier authored
Put DT_SDMMC2_COMPAT under #ifndef. Keep the default value if it is not defined in platform code. Change-Id: I611baaf1fc622d33e655ee2c78d9c287baaa6a67 Signed-off-by: -
Yann Gautier authored
On STM32MP13, two new SD1 and SD2 IO compensations cells are added, for SDMMC1 and SDMMC2. They have to be managed the same way as the main compensation cell. Change-Id: Ib7aa648d65fc98e1613bfb46b0e7dd568fd21002 Signed-off-by: -
Yann Gautier authored
The nominal voltage for VDDCPU when Cortex-A7 runs at 650MHz is 1.25V on STM32MP13. VDDCORE should be set at 1.25V as well. This is necessary, as the PMIC values in its NVMEM are 1.2V. Signed-off-by: -
Yann Gautier authored
This new function pmic_voltages_init() is used to set the minimum value for STM32MP13 VDDCPU and VDDCORE regulators. This value is retrieved from device tree. Signed-off-by: -
Nicolas Le Bayon authored
This field is now declared on the 10 LSB bits on STM32MP13. Several possible values are specified in the Reference Manual, and indicate an open or closed device. Other values lead to a system panic. Change-Id: I697124a21db66a56e7e223d601aa7cf44bb183c4 Signed-off-by: -
Patrick Delaunay authored
Update USB and DFU descriptor used for STM32MP13x Signed-off-by:Patrick Delaunay <patrick.delaunay@st.com> Change-Id: I6e8111d279f49400a72baa12ff39f140d97e1c70
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Gabriel Fernandez authored
Add new clock driver for STM32MP13. Split the include file to manage either STM32MP13 or STM32MP15. Change-Id: Ia568cd12b1d5538809204f0fd2224d51e5d1e985 Signed-off-by:Gabriel Fernandez <gabriel.fernandez@st.com>
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Yann Gautier authored
Add dedicated clock and reset dt-bindings include files. The former files are renamed with stm32mp15, and the stm32mp1 file just determine through STM32MP13 or STM32MP15 flag which file to include. Signed-off-by: -
Yann Gautier authored
The IDC register from DBGMCU is duplicated in SYSCFG. As SYSCFG is always accessible, get chip ID and revision ID from there on STM32MP13. Change-Id: Ib0b6e8f68a2934a45ec0012f69db6c12a60adb17 Signed-off-by:
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- Mar 21, 2022
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Madhukar Pappireddy authored
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Yann Gautier authored
On STM32MP13, there is only 1 DDR port, hence only 1 TZC400 filter. Change-Id: I4f6750022cdaf658cd209a4bf48a6cdb0717020e Signed-off-by: -
Lionel Debieve authored
Increase the fixed regulator number that needs to be 2 for STM32MP13. Signed-off-by: -
Yann Gautier authored
The header must now include by default at least an extra padding header, increasing the size of the header to 512 bytes (0x200). This header will be placed at the end of SRAM3 by BootROM, letting the whole SYSRAM to TF-A. The boot context is now placed in SRAM2, hence this memory has to be mapped in BL2 MMU. This mapping is done for all SRAMs in a 2MB area. Change-Id: I50fcd43ecd0ba2076292b057566efe6809b9971a Signed-off-by: -
Lionel Debieve authored
Add the new field for the new header v2.0. Force MP13 platform to use v2.0. Removing unused fields in boot_api_context_t for STM32MP13. Signed-off-by:Lionel Debieve <lionel.debieve@st.com> Change-Id: Iac81aad9a939c1f305184e335e0a907ac69071df
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Yann Gautier authored
Add the IP addresses that are STM32MP13 and update the ones for which the base address has changed. Signed-off-by: -
Yann Gautier authored
Add the new part numbers and adapt the functions that use them. There is no package number in OTP as they all share the same GPIO banks. This part is then stubbed for STM32MP13. Change-Id: I13414326b140119aece662bf8d82b387dece0dcc Signed-off-by: -
Yann Gautier authored
On STM32MP13, the chip revision Z is 0x1001, contrary to STM32MP15, for which it was 0x2001. Signed-off-by: -
Yann Gautier authored
The backup register used on STM32MP15 to save the boot interface for the next boot stage was 20. It is now saved in backup register 30 on STM32MP13. Change-Id: Ibd051ff2eca7202184fa428ed57ecd4ae7388bd8 Signed-off-by: -
Yann Gautier authored
STM32MP13 is a single Cortex-A7 CPU, always return true in stm32mp_is_single_core() function. Change-Id: Icf36eaa887bdf314137eda07c5751cea8c950143 Signed-off-by: -
Yann Gautier authored
* GPIO: On STM32MP13, there are no banks GPIOJ, GPIOK and GPIOZ. * STM32MP13 is a single Cortex-A7 CPU: remove reset from MPU1 and reset from MCU traces * There is no MCU on STM32MP13. Put MCU security management under STM32MP15 flag. * The authentication feature is not supported yet on STM32MP13, put the code under SPM32MP15 flag. * On STM32MP13, the monotonic counter is managed in ROM code, keep the monotonic counter update just for STM32MP15. * SYSCFG: put registers not present on STM32MP13 under STM32MP15 flag, as the code that manages them. * PMIC: use ldo3 during DDR configuration only for STM32MP15 * Reset UART pins on USB boot is no more required. Change-Id: Iceba59484a9bb02828fe7e99f3ecafe69c837bc7 Signed-off-by:
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Yann Gautier authored
SYSRAM is only 128KB and starts at 0x2FFE0000. SRAMs are added. BL2 code and DTB sizes are also reduced to fit in 128KB. Change-Id: I25da99ef5c08f8008ff00d38248d61b6045adad4 Signed-off-by: -
Sebastien Pasdeloup authored
STM32MP13 is a variant of STM32MP1, with a single Cortex-A7, and no Cortex-M4. There is only one DDR port. SP_min is not supported, only OP-TEE can be used as monitor. STM32MP13 uses the header v2.0 format for stm32image generation for BL2. Change-Id: Ie5b0e3230c5e064fe96f3561fc5b3208914dea53 Signed-off-by: -
Nicolas Le Bayon authored
The stm32image tool is updated to manage new header v2.0 for BL2 images. Add new structure for the header v2.0 management. Adapt to keep compatibility with v1.0. Add the header version major and minor in the command line when executing the tool, as well as binary type (0x10 for BL2). Change-Id: I70c187e8e7e95b57ab7cfad63df314307a78f1d6 Signed-off-by:
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- Mar 18, 2022
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Madhukar Pappireddy authored
* changes: fix(security): apply SMCCC_ARCH_WORKAROUND_3 to A73/A75/A72/A57 fix(security): workaround for CVE-2022-23960 for Cortex-A57, Cortex-A72 fix(fvp): disable reclaiming init code by default
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- Mar 17, 2022
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This patch applies CVE-2022-23960 workarounds for Cortex-A75, Cortex-A73, Cortex-A72 & Cortex-A57. This patch also implements the new SMCCC_ARCH_WORKAROUND_3 and enables necessary discovery hooks for Coxtex-A72, Cortex-A57, Cortex-A73 and Cortex-A75 to enable discovery of this SMC via SMC_FEATURES. SMCCC_ARCH_WORKAROUND_3 is implemented for A57/A72 because some revisions are affected by both CVE-2022-23960 and CVE-2017-5715 and this allows callers to replace SMCCC_ARCH_WORKAROUND_1 calls with SMCCC_ARCH_WORKAROUND_3. For details of SMCCC_ARCH_WORKAROUND_3, please refer SMCCCv1.4 specification. Signed-off-by:
Bipin Ravi <bipin.ravi@arm.com> Signed-off-by:
John Powell <john.powell@arm.com> Change-Id: Ifa6d9c7baa6764924638efe3c70468f98d60ed7c
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Wasim Khan authored
Update WA for Errata A-050426 as Commands for PEX (PEX1..PEX6) , lnx1_e1000#0, lnx1_xfi and lnx2_xfi has been moved to PBI phase. This patch requires RCW to include PBI commands to write commands in BIST mode for PEX, lnx1_e1000, lnx1_xfi and lnx2_xfi IP blocks. Signed-off-by:Wasim Khan <wasim.khan@nxp.com> Change-Id: I27c2b055c82c0b58df83449f9082bfbfdeb65115
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